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參數(shù)資料
| 型號： | MK2049-34SITR |
| 英文描述： | 3.3 V Communications Clock PLL |
| 中文描述： | 3.3伏通信時(shí)鐘鎖相環(huán) |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MK2049-34SITR |
MK2049-34
3.3 V Communications Clock PLL
MDS 2049-34 C
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
8
Revision 121400
Loop Filter Components
The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 3 below, and as
close to the chip as possible. High quality ceramic capacitors are recommended. DO NOT use any type of
polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Another
alternative is the Panasonic PPS polymer dielectric series; their part number for the 0.1 μF cap is
ECHU1C104JB5. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have
piezolectric properties allow mechanical vibration in the system to increase the output jitter because the
mechanical energy is converted directly to voltage noise on the VCO input.
CAP2
CAP1
5.6 nF
Crystal Operation
The MK2049 operates by phase locking the input signal to a VCXO which consists of the special
recommended crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best
performance and reliability, the layout guidelines shown on the previous page must be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected
to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal.
External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To
achieve this, the layout should use short traces between the MK2049 and the crystal.
The MK2049-34 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01μF must be connected between VDD and GND pins close to the chip (especially pins 4
and 7, 15 and 17), and 33
series terminating resistors should be used on clock outputs with traces longer
than 1 inch (assuming 50
traces). The selection of additional external components is described in the
following sections.
EXTERNAL COMPONENT SELECTION
470 k
0.1 μF
Figure 3. Loop Filter Component Values
(Typical component values are shown. Contact the ICS MicroClock applications
department at (408)297-1201 for the recommended values for your application)
相關(guān)PDF資料 |
PDF描述 |
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| MK2049-35SITR | 3.3 V Communications Clock PLL |
| MK2049-36SITR | 3.3 V Communications Clock PLL |
| MK2058-01SITR | Communications Clock Jitter Attenuator |
| MK2304S-2 | ZERO DELAY, LOW SKEW BUFFER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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