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參數(shù)資料
| 型號： | MK2058-01SITR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 254K |
| 代理商： | MK2058-01SITR |
MK2058-01
COMMUNICATIONS CLOCK JITTER ATTENUATOR
VCXO AND SYNTHESIZER
IDT COMMUNICATIONS CLOCK JITTER ATTENUATOR
5
MK2058-01
REV G 051310
A “normalized” PLL loop bandwidth may be calculated as
follows:
The “normalized” bandwidth equation above does not take
into account the effects of damping factor or the second
pole. However, it does provide a useful approximation of
filter performance.
The loop damping factor is calculated as follows:
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
CS = Value of capacitor C1 in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C1 and C2 in the loop
filter:
Charge Pump Current Table
Special considerations must be made in choosing loop
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a commonly
used trace impedance), place a 33
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
. (The
optional series termination resistor is not shown in the
External Component Schematic.)
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
MK2058-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK2058-01 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
Recommended Power Supply Connection for
Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground,
shown as CL in the External Component Schematic. These
capacitors are used to adjust the stray capacitance of the
RSET
Charge Pump Current
(ICP)
1.4 M
10
A
680 k
20
A
540 k
25
A
120 k
100
A
NBW
RS ICP
×
575
×
N
-----------------------------------------
=
Damping Factor
RS
625
I
CP
×
CS
×
N
-------------------------------------------
×
=
CP
CS
20
------
=
C onnec tion to 3.3V
Pow er Plane
Ferrite
B ead
B ulk D ec oupling C apac itor
(suc h as 1
F Tantalum )
VD D Pin
0.01
F D ecoupling C apacitors
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MK2059-01 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MK2059-01SILF | 功能描述:時鐘合成器/抖動清除器 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2059-01SILFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED FRAME CLK FREQUENCY TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2059-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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