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參數(shù)資料
| 型號(hào)： | MK2069-01GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 21/21頁 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK SYNCHRONIZER 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘同步器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
VCXO AND SYNTHESIZER
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
9
MK2069-01
REV K 051310
Notes on Setting the RV, FV and SV Divider
Values
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response software
available from IDT, increasing FV or SV decreases both
bandwidth and damping factor. Many applications require
that SV = 1. In these cases, one way to decrease loop
bandwidth is to increase the value of FV, which is
accompanied by an increase in the value of RV to maintain
the same PLL frequency multiplication ratio.
However, the phase detector frequency, FPD, also needs to
be considered. FPD is equal to the input frequency divided
by the value of the RV divider. FPD should be typically at
least 20x the loop bandwidth to prevent loop modulation
(phase noise) by the phase detector frequency. The phase
detector jitter tolerance limit (use 0.4UI) and input phase
noise frequency aliasing should be considerations as well.
Example Loop Filter Component Value
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244 to satisfy wander transfer
requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer such as
the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK output
generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant.
2) This is a reduced cost and size variant of the above filter, due to the decreased size of CS. It is useful when GR-1244
compliance is not needed, such as in a network access application.
3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is GR-1244
compliant.
4) The MK2069-02 or MK2069-04 may be more suitable for this application since the VCXO feedback divider can be
increased (>128), enabling a lower bandwidth for improved jitter attenuation.
Loop Filter Capacitor Type
Loop filters must use specific types of capacitors.
Recommendations for these capacitors can be found at
www.idt.com/?app=calculators&source=support_menu.
Input MUX
The MK2069-01 incorporates an input clock multiplexer or
‘mux’ that allows selection between one of three alternate
reference inputs supplied to the device. The mux input
selection pins are asynchronous and non-latched. Please
refer to the Input MUX Selection Table on page 2. Note that
inputs ICLK0 and ICLK1 are 5V tolerant, whereas ICLK2 is
not.
Input Phase Compensation Circuit
The VCXO PLL includes a special input clock phase
compensation circuit. It is used when selecting a new
reference input that has a clock phase differing from the
Input
Clock
Xtal
Freq
(MHz)
VCLK
(MHz)
RV
Div
FV
Div
SV
Div
RSET
RS
CS
CP
Loop
BW
(-3dB)
Loop
Damp.
Passband
Peaking
Note
8 kHz
19.44
1
2430
1
1 M
Ω 560 kΩ 1 μF 4.7 nF 22 Hz
4.0
0.15dB at 1Hz
1
8 kHz
19.44
1
2430
1
1 M
Ω 560 kΩ 0.1 μF 4.7 nF 27 Hz
1.4
1.2dB at 6Hz
2
8 kHz
22.368
1
2796
1
1 M
Ω 680 kΩ 1 μF 4.7 nF 20 Hz
4.5
0.12dB at 1Hz
3
19.44 MHz
19.44
128
1
1 M
Ω 27 kΩ
1
μF
47 nF
25 Hz
0.85
1.8dB at 8Hz
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-01GITR | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
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