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參數(shù)資料
| 型號： | MK2069-02GI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 210K |
| 代理商： | MK2069-02GI |
MK2069-02
VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
13
MK2069-02
REV G 050203
Optional Crystal Shielding
The crystal and connection traces to pins X1 and X2 are
sensitive to noise pickup. In applications that especially
sensitive to noise, such as SONET or G-Bit ethernet
transceivers, some or all of the following crystal shielding
techniques should be considered. This is especially
important when the MK2069-02 is placed near high speed
logic or signal traces.
The following techniques are illustrated on the
Recommended PCB Layout drawing.
1) The metal layer underneath the crystal section should be
the ground layer. Remove all other layers that are above.
This ground layer will help shield the crystal circuit from
other system noise sources. As an alternative, all layers
underneath the crystal can be removed, however this is not
recommended if there are adjacent PCBs or nearby clock
sources that can induce noise into the unshielded crystal
circuit.
2) Cut a channel in the PCB ground plane around the crystal
area as shown. This will eliminate high frequency ground
currents that can couple into the crystal circuit.
3) Add a through-hole for the optional third lead offered by
the crystal manufacturer (case ground). The requirement for
this third lead can be made at prototype evaluation. The
crystal is less sensitive to system noise interference when
the case is grounded.
4) Add a ground trace around the crystal circuit to shield
from other active traces on the component layer.
The external crystal is particularly sensitive to other system
clock sources that are at or near the crystal frequency since
it will try to lock to the interfering clock source. The crystal
should be keep away from these clock sources.
The IDT Applications Note MAN05 may also be referenced
for additional suggestions on layout of the crystal section.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2069-03 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Clock Translator with High Multiplication |
| MK2069-03GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| MK2069-03GITR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 VCXO-BASED CLOCK TRANSLATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2069-04 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Universal Clock Translator |
| MK2069-04GI | 功能描述:IC VCXO CLK TRANSLATOR 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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