fints_ft
參數(shù)資料
型號(hào): MK20DX256ZVLL10
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 21/74頁(yè)
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 256KB 100LQFP
標(biāo)準(zhǔn)包裝: 450
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 25x16b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
32.768
kHz
fints_t
Internal reference frequency (slow clock) — user
trimmed — over fixed voltage and temperature
range of 0–70°C
31.25
38.2
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
± 0.3
± 0.6
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
± 1.5
± 4.5
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
4
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
kHz
FLL
ffll_ref
FLL reference frequency range
31.25
39.0625
kHz
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
41.94
50
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60
62.91
75
MHz
High range (DRS=11)
2560 × ffll_ref
80
83.89
100
MHz
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
23.99
MHz
4, 5
Mid range (DRS=01)
1464 × ffll_ref
47.97
MHz
Mid-high range (DRS=10)
2197 × ffll_ref
71.99
MHz
High range (DRS=11)
2929 × ffll_ref
95.98
MHz
Jcyc_fll
FLL period jitter
fVCO = 48 MHz
fVCO = 98 MHz
180
150
ps
tfll_acquire FLL target frequency acquisition time
1
ms
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
28
Freescale Semiconductor, Inc.
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