6.3.1 MCG specifications
Table 15. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) — user
trimmed — over fixed voltage and temperature
range of 0–70°C
31.25
—
38.2
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 1.5
± 4.5
%fdco
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
kHz
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
Mid range (DRS=01)
1280 × ffll_ref
40
41.94
50
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60
62.91
75
MHz
High range (DRS=11)
2560 × ffll_ref
80
83.89
100
MHz
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
—
23.99
—
MHz
Mid range (DRS=01)
1464 × ffll_ref
—
47.97
—
MHz
Mid-high range (DRS=10)
2197 × ffll_ref
—
71.99
—
MHz
High range (DRS=11)
2929 × ffll_ref
—
95.98
—
MHz
Jcyc_fll
FLL period jitter
fVCO = 48 MHz
fVCO = 98 MHz
—
180
150
—
ps
tfll_acquire FLL target frequency acquisition time
—
1
ms
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
28
Freescale Semiconductor, Inc.