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參數(shù)資料
| 型號(hào)： | MK2703SITR |
| 英文描述： | PLL Audio Clock Synthesizer |
| 中文描述： | 鎖相環(huán)音頻時(shí)鐘合成器 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 63K |
| 代理商： | MK2703SITR |
MK2703
PLL Audio Clock Synthesizer
MDS 2703 C
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 (408) 295-9800tel www.icst.com
3
Revision 062700
Printed 11/16/00
ICRO
C
LOC K
Parameter
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Conditions
Minimum
Typical
Maximum
Units
Referenced to GND
Referenced to GND
MK2703S
MK2703SI
Max of 10 seconds
7
V
V
°C
°C
°C
°C
-0.5
0
-40
VDD+0.5
70
85
260
150
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Frequency synthesis error
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Crystal Frequency
Input Crystal Accuracy
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter, short term
-65
3.13
5.50
V
V
V
V
V
V
V
V
(VDD/2)+1
VDD/2
VDD/2
(VDD/2)-1
2
0.8
IOH=-12mA
IOL=12mA
IOH=-4mA
No Load
Each output
S1, S0
All clocks
2.4
0.4
VDD-0.4
25
±50
5
mA
mA
pF
ppm
0
27.00
MHz
ppm
ns
ns
%
ps
±30
1.5
1.5
60
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
40
±190
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The MK2703 requires a minimum number of external components for proper operation. For a crystal input,
one load capacitor should be connected from each of the X1 and X2 pins to ground. The value (in pF) of
each crystal load capacitor should equal (CL-16)2, where CL is the crystal’s load (correlation) capacitance
in pF. The input crystal must be connected as close to the chip as possible. The input crystal should be a
parallel resonant, fundamental, AT cut 27 MHz. For a clock input, connect to X1 and leave X2
unconnected. Decoupling capacitors of 0.01μF should be connected between VDD and GND on pins 2
and 3, as close to the MK2703 as possible. A series termination resistor of 33
may be used for the clock
output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2703SLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PLL AUDIO CLOCK SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2703SLFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PLL AUDIO CLOCK SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2703STR | 功能描述:IC PLL AUD CLK SYNTHESIZER 8SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2704 | 制造商:ICS 制造商全稱:ICS 功能描述:PLL Audio Clock Synthesizer |
| MK2704S | 功能描述:IC PLL AUD CLK SYNTHESIZER 8SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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