參數(shù)資料
型號(hào): MK2704SLFTR
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 2/6頁(yè)
文件大小: 0K
描述: IC PLL AUD CLK SYNTHESIZER 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘合成器 - 音頻
PLL: 帶旁路
輸入: 時(shí)鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 36.864MHz
除法器/乘法器: 無(wú)/無(wú)
電源電壓: 3.13 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
MK2704
PLL AUDIO CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
IDT PLL AUDIO CLOCK SYNTHESIZER
2
MK2704
REV E 051310
Pin Assignment
8-pin (150 mil) SOIC
AUDIO CLOCK OUTPUT SELECT TABLE
Key: 0 = Connect pin directly to ground
1 = Connect pin directly to VDD
Pin Descriptions
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the MK2704
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 2 and 3. It must be
connected close to the MK2704 to minimize lead
inductance. No external power supply filtering is required for
the MK2704.
Series Termination Resistor
A 33
terminating resistor can be used next to the clock
outputs for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 16 pF. A
parallel resonant, fundamental mode, AT cut 27 MHz crystal
should be used. The device crystal connections should
include pads for small capacitors from X1 to ground and
from X2 to ground. These capacitors are used to adjust the
X1
VDD
GND
S0
27M
S1
CLK
X2
1
2
3
4
8
7
6
5
S1
S0
CLK (MHz)
0
36.864
01
Test
1
0
16.9344
1
18.432
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
XI
Crystal Connection. Connect to a 27 MHz fundamental crystal or clock.
2
VDD
Power
Connect to +3.3 V or +5 V.
3
GND
Power
Connect to ground.
4
27M
Output
27.00 MHz buffered reference clock output.
5
CLK
Output
Audio clock output per table above.
6
S1
Input
Audio clock frequency select input #1. Determines CLK output per table
above. Internal pull-up resistor.
7
S0
Input
Audio clock frequency select input #0. Determines CLK output per table
above. Internal pull-up resistor.
8
X2
XO
Crystal connection to a 27 MHz crystal, or leave unconnected for clock
output.
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