參數(shù)資料
型號: MK2732-06GITR
英文描述: Low Phase Noise VCXO+Multiplier
中文描述: 低相位噪聲壓控乘數(shù)
文件頁數(shù): 2/4頁
文件大?。?/td> 64K
代理商: MK2732-06GITR
MK2732-06
Low Phase Noise VCXO+Multiplier
PRELIMINARY INFORMATION
MDS 2732-06 C
Integrated Circuit Systems 525 Race Street San Jose CA 95126 (408) 295-9800telwww.icst.com
2
Revision 120600
Printed 12/21/00
Pin Descriptions
Key: I = Input; TI = tri-level input; O = output; P = power supply connection; VI = analog voltage input;
XI, XO = crystal pins.
Pin Assignment
Number
1
2, 3
4
5, 6, 13
7
8
9
10
11
12
14
15
16
Name
X1
VDD5
VIN
GND
S1
OE
CLK1
S0
VDDIO
CLK2
NC
REFCLK
X2
Type
XI
P
VI
P
TI
I
O
TI
P
O
-
O
XO
Description
Crystal connection. Connect to a pullable crystal of 10-14.318 MHz.
Core VDD. Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to ground.
Select input #1. Selects outputs per table above. Do not exceed VDDIO.
Output Enable. Tri-states outputs when low. Do not exceed VDDIO.
Clock Output #1 per table above. Amplitude = VDDIO.
Select input #0. Selects outputs per table above. Do not exceed VDDIO.
Input and output VDD. Connect to +3.3V or +5V. Clock amplitude matches this voltage.
Clock Output #2 per table above. Amplitude = VDDIO.
Nothing is connected internally to this pin.
Buffered crystal VCXO clock
Crystal connection. Connect to a pullable crystal of 10-14 MHz.
MK2732-06
External Components
The MK2732-06 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01μF should be connected between VDD5 and GND on pins 3 and 5, and VDDIO and
GND on pins 11 and 13, as close to the MK2732-06 as possible. A series termination resistor of 33
may
be used for each clock output. The input crystal must be connected as close to the chip as possible. The
input crystal should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load
capacitance is recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT -
consult the application note MAN05 for layout guidelines.
16
15
14
13
12
11
10
9
16 pin (173 mil) TSSOP
1
2
3
4
5
6
7
8
VDD5
VDD5
GND
GND
X2
REFCLK
X1
VIN
OE
S1
GND
CLK2
VDDIO
S0
CLK1
S1
0
0
0
M
M
M
1
1
1
S0
0
M
1
0
M
1
0
M
1
Input
13.248
13.248
13.248
13.248
13.5
13.5
13.5
Test mode
13.5
CLK1
52.992
13.248
13.248
52.992
54
54
27
-
27
CLK2
35.328
35.328
35.328
35.328
27
27
54
-
27
Refclk
off
off
on
on
off
on
on
-
on
0=connect directly to GND
M=leave unconnected (floating)
1=connect directly to VDDIO
off=output stopped low.
Clock Select Table
NC
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