參數(shù)資料
型號: MK2746GLFTR
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/6頁
文件大小: 0K
描述: IC CLK SOURCE DVD/MPEG 16-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時鐘/頻率合成器
PLL: 帶旁路
輸入: 時鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133.33MHz
除法器/乘法器: 無/無
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
MK2746
DVD/MPEG CLOCK SOURCE
VCXO AND SYNTHESIZER
IDT DVD/MPEG CLOCK SOURCE
3
MK2746
REV C 051310
External Component Selection
The MK2746 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND as close to the MK2746 as
possible. For optimum device performance, the decoupling
capacitors should be mounted on the component side of the
PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
trace (a commonly used trace
impedance) place a 33
resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20
.
Crystal Tuning Load Capacitors
For a crystal input, a parallel resonant fundamental mode
crystal should be used. Crystal capacitors must be
connected between each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL-6)*2. In this equation CL is equal to the crystal load
capacitance in pF. As an example, for a crystal with an 18 pF
load capacitance, each crystal capacitor would be 24 pF
[(18-6)*2=24].
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI the 33
series termination resistor, if
needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK2746. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2746. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
° C
Storage Temperature
-65 to +150
° C
Soldering Temperature
260
° C
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