參數(shù)資料
型號: MK30N512VLL100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 42/61頁
文件大?。?/td> 1714K
代理商: MK30N512VLL100R
Table 35. Slave mode DSPI timing (low-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Frequency of operation
6.25
MHz
DS9
DSPI_SCK input cycle time
8 x tBCLK
ns
DS10
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS11
DSPI_SCK to DSPI_SOUT valid
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
ns
DS13
DSPI_SIN to DSPI_SCK input setup
5
ns
DS14
DSPI_SCK to DSIP_SIN input hold
15
ns
DS15
DSPI_SS active to DSPI_SOUT driven
15
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
15
ns
First data
Last data
First data
Data
Last data
Data
DS15
DS10
DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 20. DSPI classic SPI timing — slave mode
6.8.3 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
25
MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
47
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