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參數(shù)資料
| 型號(hào)： | MK32VT1664A-8YC |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 16777216 Word x 64 Bit Synchronous Dynamic RAM Module (1BANK)(16M字×64位同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 16777216字× 64位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊（1BANK）（1,600字× 64位同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | MK32VT1664A-8YC |
MK32VT1664A-8YC (98.07.17)
SERIAL PRESENCE DETECT
Byte
No.
Hex Value
80
Defines the number of bytes written into
SPD memory
1
08
Total number of bytes of SPD memory
2
04
Fundamental memory type
3
0C
Number of rows
4
09
Number of columns
5
02
Number of module banks
6
40
Data width of this assembly
7
00
... Data width continuation
8
01
Voltage interface level
9
80
Cycle time (CL=3)
10
60
Access time from CLK (CL=3)
11
00
DIMM configuration type
12
80
Refresh rate / type
13
08
Primary SDRAM width
14
00
Error checking SDRAM width
15
01
Minimum CLK delay
16
8F
Burst lengths supported
17
04
Number of banks on each SDRAM
18
06
/CAS latency
19
01
/CS latency
20
01
/WE latency
21
00
SDRAM module attributes
22
0E
SDRAM device attributes : General
23
C0
Cycle time (CL=2)
24
A0
Access time from CLK (CL=2)
25
00
Cycle time (CL=1)
26
00
Access time from CLK (CL=1)
27
1E
Minimum ROW pulse width
28
10
/RAS to /RAS bank delay
29
14
/RAS to /CAS delay
30
30
Minimum /RAS precharge time
31
10
Density of each bank on module
32
20
Command and address signal input setup time
2ns
33
10
Command and address signal input hold time
34
20
Data signal input setup time
35
10
Data signal input hold time
36-61
00-00
62
12
SPD data revision code
63
4A
Checksum for byte 0-62
64-71
41, 45, 20, 20, 20, 20, 20, 20
Manufacturer’s JEDEC ID code
72
01/06
Manufacturing location
73-90
4D, 4B, 33, 32, 56, 54, 31, 36, 36,
34, 41, 2D, 38, 59, 43, 20, 20, 20
91,92
20,20
Revision code
93-125
00-00
R.F.U
126
64
Intel specification frequency
127
F5
Intel specification /CAS latency
128-255
FF-FF
Unused storage locations
Page 4/11
SPD
Remark
Notes
0
128 byte
256 byte
SDRAM
12 rows
9 columns
2 bank
64 bits
0
LVTTL
CL=3 t
CC
=8ns
CL=3 t
AC3
=6ns
None Parity
Normal / Self
x8
t
CCD
: 1 CLK
1, 2, 4, 8, F
4 banks
2, 3
0
0
CL=2 t
CC2
=12ns
CL=2 t
AC2
=10ns
Not support
Not support
t
RP
=30ns
t
RRD
=16ns
t
RCD
=20ns
t
RAS
=48ns
64MB
1ns
2ns
1ns
R.F.U
1.2
Manufacturer’s part number
MK32VT1664A-
8YC
100MHz
CLK0-3, CL=3
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