參數資料
型號: MK3721STR
廠商: IDT, Integrated Device Technology Inc
文件頁數: 3/7頁
文件大小: 0K
描述: IC VCXO DTV/SET-TOP 8-SOIC
標準包裝: 3,000
類型: 壓控晶體振蕩器(VCXO)
PLL:
輸入: 晶體
輸出: CMOS
電路數: 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 28MHz
除法器/乘法器: 無/無
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 帶卷 (TR)
MK3721
LOW COST 16.2 TO 28 MHZ 3.3 VOLT VCXO
VCXO
IDT / ICS LOW COST 16.2 TO 28 MHZ 3.3 VOLT VCXO
3
MK3721
REV E 103003
External Component Selection
The MK3721 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01
F should be connected
between VDD and GND on pins 2 and 4 as close to the
MK3721 as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50
trace (a commonly used trace impedance),
place a 33
resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20
.
Quartz Crystal
The MK3721 VCXO function consists of the external crystal
and the integrated VCXO oscillator circuit. To assure the
best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section shown must be
followed.
The oscillation frequency of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3721 incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3721 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is
14 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25°C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3721. There should be no via’s between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal. See
application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The procedure for determining the value of these capacitors
can be found in application note MAN05.
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