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參數(shù)資料
| 型號(hào)： | MK3724GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC VCXO DTV/SET-TOP 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | PLL 時(shí)鐘合成器，VCXO |
| PLL： | 帶旁路 |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 73.728MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
VCXO AND SYNTHESIZER
IDT VCXO PLUS AUDIO CLOCK FOR STB
3
MK3724
REV E 051310
External Component Selection
The MK3724 requires a minimum number of external
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND on pins 3 and 4, pins 6 and 7, and
pins 11 and 14 as close to the MK3724 as possible. For
optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
Quartz Crystal
The MK3724 VCXO function consists of the external crystal
and the integrated VCXO oscillator circuit. To assure the
best system performance (frequency pull range) and
reliability, a crystal device meeting IDT’ recommended
parameters must be used, and the layout guidelines
discussed in the following section must be followed.
See Application Note MAN05 for a full list of crystal
parameters.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3724 incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3724 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3724. There should be no via’s between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your final
layout, a frequency counter capable of about 1 ppm
resolution and accuracy, two power supplies, and samples
of the crystals which you plan to use in production. You will
also need measured initial accuracy for each crystal at the
specified crystal load capacitance (CL).
To determine the value of the crystal capacitors:
1. Connect VDD to 3.3 V. Connect pin 5 to the second power
supply. Adjust the voltage on pin 5 to 0V. Measure and
record the frequency of the CLK output.
2. Adjust the voltage on pin 5 to 3.3 V. Measure and record
the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal being
measured
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25 ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact IDT for details.) If the
centering error is more than 25 ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
Error
10
6
x
f3.3 3.0
()V ftet
arg
–
()
f
0V
f
tet
arg
–
()
+
f
tet
arg
----------------------------------------------------------------------------------------
error
xtal
–
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK3724GL | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO PLUS AUDIO CLOCK FOR STB |
| MK3724GLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK3724GLFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK3724GTR | 功能描述:IC VCXO DTV/SET-TOP 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK3724IL | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO PLUS AUDIO CLOCK FOR STB |
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