![](http://datasheet.mmic.net.cn/30000/MK40DN512ZVLK10_datasheet_2374675/MK40DN512ZVLK10_1010.png)
USBx_OTGSTAT field descriptions (continued)
Field
Description
0 The LINE_STAT_CHG bit is not yet stable.
1 The LINE_STAT_CHG bit has been debounced and is stable.
4
Reserved
This read-only bit is reserved and always has the value zero.
3
SESS_VLD
Session valid
0 The VBUS voltage is below the B session Valid threshold
1 The VBUS voltage is above the B session Valid threshold.
2
BSESSEND
B Session END
0 The VBUS voltage is above the B session End threshold.
1 The VBUS voltage is below the B session End threshold.
1
Reserved
This read-only bit is reserved and always has the value zero.
0
AVBUSVLD
A VBUS Valid
0 The VBUS voltage is below the A VBUS Valid threshold.
1 The VBUS voltage is above the A VBUS Valid threshold.
41.4.8 OTG Control Register (USBx_OTGCTL)
The OTG Control Register controls the operation of VBUS and Data Line termination
resistors.
Addresses: USB0_OTGCTL is 4007_2000h base + 1Ch offset = 4007_201Ch
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
USBx_OTGCTL field descriptions
Field
Description
7
DPHIGH
D+ Data Line pullup resistor enable
0
D+ pullup resistor is not enabled
1
D+ pullup resistor is enabled
6
Reserved
This read-only bit is reserved and always has the value zero.
5
DPLOW
D+ Data Line pull-down resistor enable
This bit should always be enabled together with bit 4 (DMLOW)
Table continues on the next page...
Memory Map/Register Definitions
K40 Sub-Family Reference Manual, Rev. 5, 8 May 2011
1010
Freescale Semiconductor, Inc.