參數(shù)資料
型號: MK40N512VMD100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 64/75頁
文件大?。?/td> 1861K
代理商: MK40N512VMD100
144
LQF
P
144
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
39
L4
DAC1_OUT/
CMP2_IN3/
ADC1_SE2
3
DAC1_OUT DAC1_OUT/
CMP2_IN3/
ADC1_SE2
3
40
M7 XTAL32
XTAL32
41
M6 EXTAL32
EXTAL32
42
L6
VBAT
43
VDD
44
VSS
45
M4 PTE24
ADC0_SE1
7
ADC0_SE1
7
PTE24
CAN1_TX
UART4_TX
EWM_OUT
_b
46
K5 PTE25
ADC0_SE1
8
ADC0_SE1
8
PTE25
CAN1_RX
UART4_RX
FB_AD23
EWM_IN
47
K4 PTE26
DISABLED
PTE26
UART4_CT
S_b
FB_AD22
RTC_CLKO
UT
USB_CLKIN
48
J4
PTE27
DISABLED
PTE27
UART4_RT
S_b
FB_AD21
49
H4 PTE28
DISABLED
PTE28
FB_AD20
50
J5
PTA0
JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CT
S_b
FTM0_CH5
JTAG_TCL
K/
SWD_CLK
EZP_CLK
51
J6
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX FTM0_CH6
JTAG_TDI
EZP_DI
52
K6 PTA2
JTAG_TDO/
TRACE_SW
O/EZP_DO
TSI0_CH3
PTA2
UART0_TX FTM0_CH7
JTAG_TDO/
TRACE_SW
O
EZP_DO
53
K7 PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
UART0_RT
S_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
54
L7
PTA4
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4
FTM0_CH1
NMI_b
EZP_CS_b
55
M8 PTA5
DISABLED
PTA5
FTM0_CH2
CMP2_OUT I2S0_RX_B
CLK
JTAG_TRS
T
56
E7 VDD
VDD
57
G7 VSS
VSS
58
J7
PTA6
DISABLED
PTA6
FTM0_CH3
FB_CLKOU
T
TRACE_CL
KOUT
59
J8
PTA7
ADC0_SE1
0
ADC0_SE1
0
PTA7
FTM0_CH4
FB_AD18
TRACE_D3
60
K8 PTA8
ADC0_SE1
1
ADC0_SE1
1
PTA8
FTM1_CH0
FB_AD17
FTM1_QD_
PHA
TRACE_D2
61
L8
PTA9
DISABLED
PTA9
FTM1_CH1
FB_AD16
FTM1_QD_
PHB
TRACE_D1
62
M9 PTA10
DISABLED
PTA10
FTM2_CH0
FB_AD15
FTM2_QD_
PHA
TRACE_D0
63
L9
PTA11
DISABLED
PTA11
FTM2_CH1
FB_OE_b
FTM2_QD_
PHB
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
67
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