參數(shù)資料
型號: MK40N512VMD100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 16/75頁
文件大小: 1861K
代理商: MK40N512VMD100R
6.1.2 JTAG electricals
Table 11. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
J1
TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
10
25
50
MHz
J2
TCLK cycle period
1/J1
ns
J3
TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
20
10
ns
J4
TCLK rise and fall times
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
ns
J6
Boundary scan input data hold time after TCLK rise
0
ns
J7
TCLK low to boundary scan output data valid
25
ns
J8
TCLK low to boundary scan output high-Z
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
ns
J10
TMS, TDI input data hold time after TCLK rise
1
ns
J11
TCLK low to TDO data valid
17
ns
J12
TCLK low to TDO high-Z
17
ns
J13
TRST assert time
100
ns
J14
TRST setup time (negation) to TCLK high
8
ns
Table 12. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
10
20
40
MHz
J2
TCLK cycle period
1/J1
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
23
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MK40N512VMD100 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
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