參數(shù)資料
型號: MK41T56N00
廠商: 意法半導體
英文描述: 512 bit 64b x8 Serial Access TIMEKEEPER SRAM
中文描述: 512位64B條x8串行SRAM的訪問計時器
文件頁數(shù): 3/15頁
文件大小: 102K
代理商: MK41T56N00
Data retention time is in excess of 10 years with a
50mAh 3V lithium cell. The MK41T56 is supplied in
8 pin Plastic Dual-in-Line and 8 lead Plastic SOIC
packages.
OPERATION
The MK41T56 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (11010000). The 64 bytes contained in the
device can then be accessed sequentially in the
following order:
1.
Seconds Register
2.
Minutes Register
3.
Hours Register
4.
Day Register
5.
Date Register
6.
Month Register
7.
Years Register
8.
Control Register
9 to 64.
RAM
DESCRIPTION
(cont’d)
AI01019
5V
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI00586C
SECONDS
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
(56 x 8)
OSCI
OSCO
FT/OUT
VCC
VSS
VBAT
SCL
SDA
1 Hz
Figure 3. Block Diagram
3/15
MK41T56, MKI41T56
相關(guān)PDF資料
PDF描述
MK41T56N00TR 512 bit 64b x8 Serial Access TIMEKEEPER SRAM
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