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參數(shù)資料
| 型號(hào)： | MK5027DIP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SS7 SIGNALLING LINK CONTROLLER |
| 中文描述： | 七號(hào)信令鏈路控制器 |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大?。?/td> | 183K |
| 代理商： | MK5027DIP |
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Table 1:
PinDescription.
LEGEND:
I
IO
OD
Input only
Input/Output
Open Drain (no internal pull-up)
O
3S
Output only
3-State
Signal Name
DAL<15:00>
Pin(s)
2-9
40-47
Type
IO/3S
Descriplion
The time multiplexed Data Address bus.During the address portion of a
memory transfer, DALe15:00 contains the lower 16 bits of the memory
address.
Duringthe data portion of a memory transfer, DAL<15:00> contains the
read or write data, depending on the type of transfer.
READ indicates the type of operation that the bus controlleris performing
during a bus transaction. READ is driven by the MK5027 only while it is
the BUS MASTER. READ is valid during the entire bus transaction and is
tristated at all other times.
MK5027 as a Bus Slave:
READ = HIGH - Data is placed onthe DAL lines by the chip.
READ = LOW - Data is taken off the DAL lines by the chip.
MK5027 as a Bus Master:
READ = HIGH - Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.
INTERRUPT is an attention interrupt line that indicates that one or more of
the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.
INTERRUPT is enabled by CSR0<0.9>, INEA = 1.
DAL IN is an external bus transceiver control line. DALIis driven by the
MK5027 only while it is the BUS MASTER. DALIis asserted by the
MK5027 when | ads from the DAL lines during the data portion of a READ
transfer. DALIis not asserted during a WRITE transfer.
DAL OUT is an external bus transceiver control line. DALOis driven by
the MK5027 only while it isthe BUS MASTER. DALOis asserted by the
MK5027 when it drives the DAL linesduring the address portion of a
READ transfer or for the duration of a WRITE transfer.
DATA STROBE defines the data portio,n ofa transaction. By definition,
data is stable and valid at the low to high transition of DAS.This signal is
driven by the MK5027 while it is the BUS MASTER. During the BUS
SLAVE operation, this pin is used as an input. At all other times the signal
is tristated.
I/O pins 15and 16 are programmable through CSR4. If bit 06 of CSR4 is
set to a one, pin 15 becomes input BUSRELand is used by the hostto
signalthe MK5027 to terminate a DMA burst after the current bus transfer
has completed. If bit 06 is clearthe pin 15 is an output and behaves as
described below for pin 16.
READ
10
IO/3S
INTR
11
O/OD
DALI
12
O/3S
DALO
13
O/3S
DAS
14
IO/3S
BMO
BYTE
BUSREL
15
IO/3S
Note:
Pin out shown is for 48 pin dip.
MK5027
2/19
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