參數(shù)資料
型號: MK60X256VLL100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 63/73頁
文件大?。?/td> 1815K
代理商: MK60X256VLL100
8.1 K60 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 81-pin ballmap assignments are currently being developed.
The in the entries in this package column indicate which
signals are present on the package.
100
LQF
P
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
1
PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
I2C1_SDA
2
PTE1
ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX
SDHC0_D0
I2C1_SCL
3
PTE2
ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK
UART1_CTS
_b
SDHC0_DCL
K
4
PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS
_b
SDHC0_CM
D
5
PTE4
DISABLED
PTE4
SPI1_PCS0
UART3_TX
SDHC0_D3
6
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
7
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_CTS
_b
I2S0_MCLK
I2S0_CLKIN
8
VDD
9
VSS
10
USB0_DP
11
USB0_DM
12
VOUT33
13
VREGIN
14
ADC0_DP1
15
ADC0_DM1
16
ADC1_DP1
17
ADC1_DM1
18
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
19
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
20
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
21
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
22
VDDA
23
VREFH
Pinout
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
66
Preliminary
Freescale Semiconductor, Inc.
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