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參數(shù)資料
| 型號： | MK74ZD133YLFT |
| 元件分類： | 時鐘及定時 |
| 英文描述： | ZD SERIES, PLL BASED CLOCK DRIVER, 32 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MK74ZD133YLFT |
MK74ZD133
PLL and 32-Output Clock Driver
PRELIMINARY
PRELIMINARY INFORMATION
INFORMATION
MDS 74ZD133 C
6
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
C
Soldering Temperature
Max of 10 seconds
260
C
Storage Temperature
-65
150
C
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
3.15
3.3
3.45
V
Required External VDD Power Supply Ramp
To 90% VDD
0.1
50
ms
Input High Voltage, VIH (S0-S4, OE)
2.0
V
Input Low Voltage, VIL (S0-S4, OE)
0.8
V
Output High Voltage
IOH=-4mA
VDD-0.4
V
Output High Voltage
IOH=-12mA
2.4
V
Output Low Voltage
IOL=12mA
0.8
V
Operating Supply Current, IDD, at 66.6 MHz
No Load, F package
135
mA
Operating Supply Current, IDD, at 133 MHz
No Load, Y package
270
mA
Short Circuit Current at 3.3V
Each output
±35
mA
Input Capacitance
OE, FBIN, CLKIN
5
pF
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Clock Frequency
See page 5
3
80
MHz
Output Clock Frequency, F package
80
MHz
Output Clock Frequency, Y package
Note 2.
133.34
MHz
Input to Output skew, Rising Edges at VDD/2
Zero Delay Mode, nt. 3
±100
±350
ps
Device to Device skew, VDD/2, ZD mode
OUT1 to OUT1
700
ps
Output to Output skew, Rising Edges at VDD/2
Plus offsets
±150
see pages 4,5
ps
Output Clock Rise Time, into 33
and 15pF
0.8 to 2.0V
1.5
2
ns
Output Clock Fall Time, into 33
and 15pF
2.0 to 0.8V
1.5
2
ns
Total Capacitive Load on all outputs, still air
133 MHz
320
pf
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Assumes maximum of 10 pF loads on all outputs in still air, and a thermal ground pad under the LQFP. For 15 pF loads on each
output, air circulation of TBD must be present.
3. From CLKIN to OUT1
External Components
The MK74ZD133 requires some inexpensive external components for proper operation.
Decoupling
capacitors of 0.01F should be connected on each VDDxx pin to ground, as close to the device as possible
(adjacent VDDs can be connected together). A series termination resistor of 33
must be used for each
clock output. See the discussion on page 5 for other external resistors required for proper I/O operation.
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