參數(shù)資料
型號(hào): ML2008IQ
英文描述: レP Compatible Logarithmic Gain/Attenuator
中文描述: レP兼容的對(duì)數(shù)增益/衰減器
文件頁(yè)數(shù): 1/11頁(yè)
文件大小: 155K
代理商: ML2008IQ
March 1997
ML2008
*
, ML2009
**
μ
P Compatible Logarithmic Gain/Attenuator
FEATURES
I
Low noise
I
Low harmonic distortion
I
Gain range
I
Resolution
I
Flat frequency response
0dBrnc max with +24dB gain
–60dB max
–24 to +24dB
0.1dB steps
±
0.05dB from 0.3-4kHz
±
0.10dB from 0.1-20kHz
4mA max from
±
5V supplies
I
Low supply current
I
TTL/CMOS compatible digital interface
I
ML2008 is designed to interface to an 8-bit data bus;
ML2009 to 16-bit data bus
GENERAL DESCRIPTION
The ML2008 and ML2009 are digitally controlled
logarithmic gain/attenuators with a range of –24 to +24dB
in 0.1dB steps.
Easy interface to microprocessors is provided by an input
latch and control signals consisting of chip select and
write.
The interface for gain setting of the ML2008 is by an 8-bit
data word, while the ML2009 is designed to interface to a
16-bit data bus with a single write operation by hard-
wiring the gain/attenuation pin or LSB pin. The ML2008
can be power downed by the microprocessor utilizing a
bit in the second write operation.
Absolute gain accuracy is 0.05dB max over supply
tolerance of
±
10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for
* This Part Is End Of Life As Of August 1, 2000
a wide variety of applications in telecom, audio, sonar or
** This Part Is Obsolete
general purpose function generation.
BLOCK DIAGRAM
+
COARSE
+
+
BUFFER
RESISTORS/
SWITCHES
RESISTORS/
SWITCHES
V
CC
V
SS
GND
AGND
V
IN
FINE
V
OUT
16
16
+5
–5
DECODERS
WR
CS
A0
REGISTER 0
REGISTER 1
8
1
1
PDN
D1–D8
8
+
COARSE
+
+
BUFFER
RESISTORS/
SWITCHES
RESISTORS/
SWITCHES
V
CC
V
SS
GND
AGND
V
IN
FINE
V
OUT
16
16
+5
–5
DECODERS
REGISTER 0
9
D0–D8
9
WR
CS
ML2008
ML2009
*
1
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