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參數資料
| 型號： | ML2037 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 500kHz, Serial Input, Programmable Sine Wave Generator with Digital Gain Control(500kHz、數字增益控制的串行輸入可編程正弦波發(fā)生器) |
| 中文描述： | 為500kHz，串行輸入，可編程正弦波發(fā)生器數字增益控制（為500kHz，數字增益控制的串行輸入可編程正弦波發(fā)生器） |
| 文件頁數： | 5/10頁 |
| 文件大?。?/td> | 213K |
| 代理商： | ML2037 |
ML2037
REV. 1.0 10/10/2000
5
FUNCTIONAL DESCRIPTION
The ML2037 is composed of a programmable frequency
generator, a sine wave generator, a crystal oscillator, and
a digital interface. The functional block diagram is shown
in Figure 1.
PROGRAMMABLE FREQUENCY GENERATOR
The programmable frequency generator produces a digital
output whose frequency is determined by a 16-bit digital
word.
The frequency generator is composed of a phase
accumulator which is clocked at f
CLK IN
. The value
stored in the data latch is added to the phase accumulator
every two cycles of CLK IN. The frequency of the analog
output is equal to the rate at which the accumulator
overflows and is given by the following equation:
(1)
Where (D15–D0) is the decimal value of the programming
word.
The frequency resolution and the minimum frequency are
the same and can be calculated using:
(2)
When f
CLK IN
= 25MHz,
f
MIN
= 5.96Hz (
±
2.98Hz).
Lower output frequencies are obtained by using a lower
clock frequency.
The maximum frequency output can be easily calculated
with the following equation:
(3)
When f
CLK IN
= 25MHz, f
OUT(MAX)
= 391kHz. Higher
frequencies, up to 500kHz, are obtained by using an
external clock, where 25MHz < f
CLK IN
< 32MHz.
Due to the phase quantization nature of the frequency
generator, spurious tones can be present in the output in
the range of –50dB relative to fundamental. The energy
from these tones is included in the signal to noise +
distortion specification (SND) given in the electrical
table. The frequency of these tones can be very close to
the fundamental, and it is not practical to filter them out.
SINEWAVE GENERATOR
The sinewave generator is composed of a sine lookup
table, an 8-bit DAC, an output smoothing filter, and an
amplifier. The sine lookup table is addressed by the phase
accumulator. The DAC is driven by the output of the table
and generates a staircase representation of a sine wave.
The output filter smooths the analog output by removing
the high frequency sampling components. The resultant
voltage on V
OUT
is a sinusoid with the second and third
harmonic distortion components at least 40dB below the
fundamental.
The ML2037 has a 2-bit (G1, G0) digital gain control.
With the gain input equal to logic 00, the sine wave
amplitude is equal to 0.5V
P-P
. Incrementing the gain
control input increases the output amplitude in 0.5V steps
to a maximum of 2.0V
P-P
. The output amplitude is
accurate to within
±
0.5dB over the frequency range.
G1
0
0
1
1
G0
0
1
0
1
P–P OUTPUT AMPLITUDE
.5V
1.0V
1.5V
2.0V
The analog section is designed to operate over a
frequency range of DC to 500kHz and is capable of
driving 1k
, 50pF loads at the maximum amplitude of
2.0V
P-P
. The sine wave output is typically centered about
a 2.5V DC level, so for a 2V
P-P
sine wave, the output will
swing from 1.5V to 3.5V.
CRYSTAL OSCILLATOR
The crystal oscillator generates an accurate reference
clock for the programmable frequency generator. The
internal clock can be generated with a crystal or external
clock.
If a crystal is used, it must be placed between CLK IN and
DGND. An on-chip oscillator will then generate the
internal clock. No other external components are
required. The crystal should be a parallel resonant type
with a frequency between 5MHz to 25.6MHz. It should
be placed physically as close as possible to CLK IN and
DGND, to minimize trace lengths.
The crystal must have the following characteristics:
Parallel resonant type
Frequency: 5MHz to 25.6MHz
Maximum ESR: 120
@ 5 to 10MHz, 80
@10 to
15MHz, and 50
@ 15 to 25.6MHz
Drive level: 500
μ
W
Typical load capacitance: 18 - 20pF
Maximum case capacitance: 7pF
The frequency of oscillation will be a function of the
crystal parameters and board capacitance. In general,
f
f
f
MIN
CLKIN
2
22
f
f
OUT MAX
(
CLKIN
2
6
)
f
CLKIN
×
(D15
→
D0)
DEC
2
22
OUT
=
=
=
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