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參數(shù)資料
| 型號(hào)： | ML2259BCP |
| 元件分類(lèi)： | 串行ADC |
| 英文描述： | レP Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer |
| 中文描述： | レP兼容的8位A / D轉(zhuǎn)換器2 -或8通道多路復(fù)用器 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大小： | 202K |
| 代理商： | ML2259BCP |
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ML2252, ML2259
10
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies,
f
A
and f
B
, any active device with nonlinearities will
create distortion products, of order (m + n), at sum and
difference frequencies of mf
A
+ nf
B
, where m, n = 0, 1, 2,
3,... . Intermodulation terms are those for which m or n is
not equal to zero. The (IMD) intermodulation distortion
specification includes the second order terms (f
A
+ f
B
) and
(f
A
– f
B
) and the third order terms (2f
A
+ f
B
), (2f
A
– f
B
),
(f
A
+ 2f
B
) and (f
A
– 2f
B
) only.
1.7 DIGITAL INTERFACE
The analog inputs are selected by the digital addresses,
ADDR0–ADDR2, and latched on the rising edge of ALE.
This is described in the Multiplexer Addressing section.
A conversion is initiated by the rising edge of a START
pulse. As long as this pulse is high, the internal logic is
reset.
The sampling interval starts with the following CLK rising
edge after a START falling edge and ends on the falling
edge of CLK. The conversion starts and EOC goes low. The
sampling clock is at least one half CLK period wide. Each
bit conversion in the successive approximation process
takes 1 CLK period. On the rising edge of the ninth CLK
pulse, the digital output of the conversion is updated on
the outputs DB0–DB7 and EOC goes high indicating the
conversion is done and data on DB0–DB7 is valid.
One feature of the ML2252 and ML2259 is that the data is
double buffered. This means that the outputs DB0–DB7
will stay valid until updated at the end of the next
conversion and will not become invalid when the next
conversion starts. This facilitates interfacing with external
logic of μP.
The signal OE drives the data bus, DB0–DB7, into the
high impedance state when held low. This allows the
ML2252 and ML2259 to be tied directly to a μP system
bus without any latches or buffers.
1.7.1 Restart During Conversion
If the A/D is restarted (start goes low and returns high)
during a convesion, the converter is reset and a new
conversion is started. The output data latch is not updated
if the conversion in process is not allowed to be
completed. EOC will remain low and the output data
latch is not updated.
1.7.2 Continuous Conversions
In the free-running, continuous conversion mode, the start
input is tied to the (figure 7) EOC output. An initialization
pulse, following power-up, of mementarily forcing a logic
high level is required to guarantee operation.
Figure 8. Protecting the Input
Figure 9. Operating with Ratiometric Transducers 15% of
V
CC
- V
XDR
- 85% of V
CC
2.0 TYPICAL APPLICATIONS
Figure 7. Continuous Conversion Mode
START
EOC
ML2252
ML2259
V
CC
START
+
–
15V
DC
–15V
DC
600
V
CC
GND
V
CC
ANALOG
IN
ML2252
ML2259
10
μ
F
+
V
CC
(5V
DC
)
–V
REF
V
CC
CH
ML2252
ML2259
10
μ
F
+
20k
3k
XDR
+VREF
0.15V
CC
+
–
0.85V
CC
4k
1k
24k
+
–
FS
ADJ
ZERO ADJ
1k
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML2259BCQ | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:レP Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer |
| ML2259CCP | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:レP Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer |
| ML2259CCQ | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:レP Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer |
| ML2261 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:レP Compatible High-Speed 8-Bit A/D Converter with T/H (S/H) |
| ML2261BCP | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:レP Compatible High-Speed 8-Bit A/D Converter with T/H (S/H) |
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