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參數(shù)資料
| 型號： | ML2330ES-5 |
| 英文描述： | Selectable Dual 3V/3.3V/5V 8-Bit DACs |
| 中文描述： | 可選雙3V/3.3V/5V 8位DAC |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 210K |
| 代理商： | ML2330ES-5 |
ML2330
5
The 4-bit address/control code configures the DAC as
shown in Table 1.
A1
A0
Function
0
0
No operation
0
1
Select control bits and DAC A
1
0
Select control bits and DAC B
1
1
Select control bits and both DACs
Table 1.1 Address Selection
P1
P0
Function
0
0
Normal
0
1
Power down DAC A
1
0
Power down DAC B
1
1
Power down entire chip
Table 1.2 Power Down Selection
DAC OPERATION
The DACs are implemented using an array of equal
current sources that are decoded linearly for the four most
significant bits to improve differential linearity and to
reduce output glitch around major carries. A voltage
difference between on-board bandgap reference voltage
and GND is converted to a reference current using an
internal resistor to set up the appropriate current level in
the DACs. The DACs output current is then converted to a
voltage output by an output buffer and a resistive network.
The matching among the on-chip resistors preserves the
gain accuracy between these conversions.
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The ML2330 communicates with microprocessors through
a synchronous, full-duplex, 3-wire interface (figure 1A &
B). At power on, the control registers are cleared and both
DACs have high impedance outputs. Data timing shown
in Figure 1C is sent MSB-first and can be transmitted in
one 4-bit and one 8-bit packet or in one 12-bit word. If a
16-bit control word is used, the first four bits are ignored.
The serial clock (S
CLK
) synchronizes the data transfer. Data
is transmitted and received simultaneously. Figure 2 shows
detailed serial interface timing. Note that the clock should
be low between updates. D
OUT
does not go into a high
impedance state if the clock idles or
CS
is high.
Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is sampled on the
S
CLK
’s rising edge while
CS
is low. Data at D
OUT
is
clocked out 12.5 clock cycles later, on the S
CLK
’s falling
edge.
Chip Select (
CS
) must be low to enable the read or write
operation. If
CS
is high, the interface is disabled and D
OUT
remains unchanged.
CS
must go low at least 10ns before
the first clock pulse to properly clock in the first bit. With
CS
low, data is clocked into the ML2330’s internal shift
register on the rising edge of the external serial clock. S
CLK
can be driven at rates up to 10MHz.
SERIAL INPUT DATA FORMAT AND
CONFIGURATION CODES
The 12-bit serial input format shown in Figure 3 comprises
two DAC address bits (A1, A0), two power down control
bits (P1, P0) and eight bits of data (D7 . . . D0).
DOUT
A1 A0 P1 D7 . . . D0
DIN
Figure 3. Serial Input Format
Figure 2. Detail Interface Timing
CS
S
CLK
D
IN
D
OUT
t
CSS
t
DS
t
DH
t
DO
t
CSH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML2330IS-2 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Selectable Dual 3V/3.3V/5V 8-Bit DACs |
| ML2330IS-3 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Selectable Dual 3V/3.3V/5V 8-Bit DACs |
| ML2330IS-5 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Selectable Dual 3V/3.3V/5V 8-Bit DACs |
| ML2340 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Single Supply, Programmable 8-Bit D/A Converters |
| ML2340CCP/12 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Single Supply, Programmable 8-Bit D/A Converters |
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