參數(shù)資料
型號: ML4803IS-1
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: 8-Pin PFC and PWM Controller Combo
中文描述: 1 A POWER FACTOR CONTROLLER WITH POST REGULATOR, 67 kHz SWITCHING FREQ-MAX, PDSO8
封裝: SOIC-8
文件頁數(shù): 8/13頁
文件大?。?/td> 195K
代理商: ML4803IS-1
ML4803
8
February 1999
Figure 4. Voltage Control Loop
60
40
20
0
20
40
60
G
FREQUENCY (Hz)
0.1
10
1000
1
100
Power Stage
Overall Gain
Compensation
Network Gain
0
50
100
150
200
P
o
)
FREQUENCY (Hz)
0.1
1
10
1000
100
Power Stage
Overall
Compensation
Network
Figure 5. Voltage Loop Gain
Figure 6. Voltage Loop Phase
50
40
30
20
10
0
I
VEAO (V)
0
2
7
5
1
3
6
4
FF @
55
o
C
TYP @
55
o
C
TYP @ 155
o
C
SS @ 155
o
C
TYP @ ROOM TEMP
Figure 7. Internal Ramp Current vs. V
EAO
R
C
COMP
COMP
=
′ ′
1
2
p
(3)
R
Hz
nF
k
COMP
=
=
1
628
.
30
16
330
W
C
f
R
ZERO
COMP
=
1
2
10
p
(4)
C
Hz
3
k
F
ZERO
=
=
1
628
.
330
016
.
W
m
INTERNAL VOLTAGE RAMP
The internal ramp current source is programmed by way of
the VEAO pin voltage. Figure 7 displays the internal ramp
current vs. the VEAO voltage. This current source is used
to develop the internal ramp by charging the internal
30pF +12/
10% capacitor. See Figures 10 and 11. The
frequency of the internal programming ramp is set
internally to 67kHz.
PFC CURRENT SENSE FILTERING
In DCM, the input current wave shaping technique used
by the ML4803 could cause the input current to run away.
In order for this technique to be able to operate properly
under DCM, the programming ramp must meet the boost
inductor current down-slope at zero amps. Assuming the
programming ramp is zero under light load, the OFF-time
will be terminated once the inductor current reaches zero.
Subsequently the PFC gate drive is initiated, eliminating
the necessary dead time needed for the DCM mode. This
forces the output to run away until the V
CC
OVP shuts
down the PFC. This situation is corrected by adding an
TYPICAL APPLICATIONS
(Continued)
ML4803
ML4803
IVEAO
35μA
IOUT
VO
220μF
RLOAD
667
330k
11.3M
0.15μF
15nF
POWER
STAGE
COMPENSATION
VEAO
VEAO +
相關(guān)PDF資料
PDF描述
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