參數(shù)資料
型號(hào): ML4810
廠商: Fairchild Semiconductor Corporation
英文描述: High Frequency PWM Controller(高頻PWM控制器)
中文描述: 高頻PWM控制器(高頻脈寬調(diào)制控制器)
文件頁(yè)數(shù): 4/11頁(yè)
文件大?。?/td> 196K
代理商: ML4810
ML4810, ML4811
4
REV. 1.0 10/10/2000
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
(Continued)
CMRR
PSRR
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth
Slew Rate
1.5 < V
CM
< 5.5V
10 < V
CC
< 30V
V
PIN 3
= 1V
V
PIN 3
= 4V
I
PIN 3
= –0.5mA
I
PIN 3
= 1mA
65
75
1
–0.5
4.0
0
3
6
95
90
2.5
–1.3
4.7
0.5
5.5
12
dB
dB
mA
mA
V
V
MHz
V/
μ
s
5.0
1.0
PWM COMPARATOR
Pin 8 Bias Current
Duty Cycle Range
Pin 3 Zero DC Threshold
Delay to Output
V
PIN 8
= 0V
–1
–5
75
μ
A
%
V
ns
0
1.1
1.25
50
80
SOFT-START
Charge Current (Pin 9)
Discharge Current (Pin 9)
ML4811
V
PIN 9
= 1V, V
PIN 4
,
12
= 0
V
PIN 9
= 3V, V
PIN 4
> 2.5
V
PIN 9
= 3V, V
PIN 12
> 1.65, V
PIN 4
< 2
V
PIN 20
= 1V
Requires external discharge resistor
–35
1
1
1
–55
5
5
5
0
–75
μ
A
mA
mA
mA
μ
A
Charge Current (Pin 20)
Discharge Current (Pin 20)
CURRENT LIMIT/SHUTDOWN
Pin 12 Bias Current
Current Limit Threshold
0V < V
PIN 12
< 4V
+15
1.4
1.3
1.90
1.8
70
180
3
2.8
60
–60
μ
A
V
V
V
V
ns
μ
A
V
V
μ
A
μ
A
ML4810
ML4811
ML4810
ML4811
1.2
0.95
1.60
1.4
1.3
1.1
1.75
1.50
40
150
2.45
2.7
50
–50
Reset Threshold (Pin 12)
V
PIN 4
< 2V
V
PIN 4
< 2V
Delay to Output
Pin 4 Charging Current
Restart Threshold (Pin 4)
OVP Shutdown Threshold (Pin 11)
OVP Input Current
Charge Current (Pin 8)
V
PIN 12
= 2V
120
2
2.4
40
–40
V
PIN 11
= 3V
V
PIN 8
= 1V, V
PIN 4, 9
= 0
ML4810
OUTPUT
Output Low Level
I
OUT
= 20mA
I
OUT
= 200mA
I
OUT
= –20mA
I
OUT
= –200mA
V
C
= 30V
C
L
= 1000pF
0.25
0.4
V
1.2
2.2
V
Output High Level
13.0
13.5
V
12.0
13.0
V
μ
A
Collector Leakage
100
500
Rise/Fall Time
30
60
ns
SUPPLY
Start Up Current
ML4810
ML4811
ML4810
ML4811
V
CC
= 8V
V
CC
= 8V
V
PIN 1, 7, 9
= 0V, V
PIN 2
= 1V, T
A
= 25
°
C
V
PIN 1, 7, 9
= 0V, V
PIN 2
= 1V, T
A
= 25
°
C
2.0
2.5
32
38
3.5
4.0
46
55
mA
mA
mA
mA
I
CC
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
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