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參數(shù)資料
| 型號： | ML4824CS-1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Power Factor Correction and PWM Controller Combo |
| 中文描述： | 0.5 A POWER FACTOR CONTROLLER WITH POST REGULATOR, 250 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 262K |
| 代理商： | ML4824CS-1 |
ML4824
9
FUNCTIONAL DESCRIPTION
(Continued)
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4824’s voltage error amplifier has a
specially shaped nonlinearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbations in
line or load conditions will cause the input to the voltage
error amplifier (V
FB
) to deviate from its 2.5V (nominal)
value. If this happens, the transconductance of the voltage
error amplifier will increase significantly, as shown in the
Typical Performance Characteristics. This raises the gain-
bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristic.
The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.
For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.
Oscillator (RAMP 1)
The oscillator frequency is determined by the values of R
T
and C
T
, which determine the ramp and off-time of the
oscillator output clock:
f
t
t
OSC
RAMP
DEADTIME
=
+
1
(2)
The deadtime of the oscillator is derived from the
following equation:
t
C
R
In
V
V
RAMP
T
T
REF
REF
=
′
′
-
-
F
I
125
375
.
.
(3)
at V
REF
= 7.5V:
t
C
R
RAMP
T
T
=
′
′
051
.
The deadtime of the oscillator may be determined using:
t
V
mA
C
C
DEADTIME
T
T
=
′
=
′
25
.
51
.
490
(4)
The deadtime is so small (t
RAMP
>> t
DEADTIME
) that the
operating frequency can typically be approximated by:
f
t
OSC
RAMP
=
1
(5)
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
f
kHz
t
OSC
RAMP
=
=
100
1
t
C
R
RAMP
T
T
=
′
′
= ′
-
0 51 1 10
.
5
Solving for R
T
x C
T
yields 2 x 10
-4
. Selecting standard
components values, C
T
= 470pF, and R
T
= 41.2k
.
The deadtime of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator deadtime, the Maximum PWM Duty Cycle
is typically 45%. In many applications, care should be
taken that C
T
not be made so large as to extend the
Maximum Duty Cycle beyond 50%. This can be
accomplished by using a stable 470pF capacitor for C
T
.
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4824 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4824-1, and at
twice the PFC frequency in the ML4824-2). The PWM is
capable of current-mode or voltage mode operation. In
current-mode applications, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the
converter’s output stage. DC I
LIMIT
, which provides cycle-
by-cycle current limiting, is typically connected to RAMP
2 in such applications. For voltage-mode operation or
certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which V
DC
will be compared. Under
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC I
LIMIT
input is used for output stage overcurrent protection.
相關PDF資料 |
PDF描述 |
|---|---|
| ML4824CP-1 | Power Factor Correction and PWM Controller Combo |
| ML4824IS-2 | Power Factor Correction and PWM Controller Combo |
| ML4824IS-1 | Power Factor Correction and PWM Controller Combo |
| ML4826CP-1 | PFC and Dual Output PWM Controller Combo |
| ML4826CP-2 | PFC and Dual Output PWM Controller Combo |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ML4824CS1 | 制造商:Fairchild Semiconductor Corporation 功能描述:PFC/PWM CONTROLLER 4824 SOIC16 |
| ML4824CS1_Q | 功能描述:功率因數(shù)校正 IC PFC Controller PWM Combo RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| ML4824CS1X | 功能描述:功率因數(shù)校正 IC PFC Controller PWM Combo RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| ML4824CS2 | 功能描述:功率因數(shù)校正 IC PFC Controller PWM Combo RoHS:否 制造商:Fairchild Semiconductor 開關頻率:300 KHz 最大功率耗散: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Reel |
| ML4824CS-2 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Power Factor Correction and PWM Controller Combo |
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