![](http://datasheet.mmic.net.cn/30000/ML610Q409-NNNTBZ03A_datasheet_2374756/ML610Q409-NNNTBZ03A_6.png)
ML610Q407/ML610Q408/ML610Q409 User’s Manual
Contents
Contents –1
Chapter 4
4. MCU Control Function......................................................................................................................................................... 4-1
4.1 Overview ...................................................................................................................................................................... 4-1
4.1.1
Features................................................................................................................................................................. 4-1
4.1.2
Configuration........................................................................................................................................................ 4-1
4.2 Description of Registers ............................................................................................................................................... 4-2
4.2.1
List of Registers .................................................................................................................................................... 4-2
4.2.2
Stop Code Acceptor (STPACP) ............................................................................................................................ 4-3
4.2.3
Standby Control Register (SBYCON) .................................................................................................................. 4-4
4.2.4
Block Control Register 0 (BLKCON0) ................................................................................................................ 4-5
4.2.5
Block Control Register 1 (BLKCON1) ................................................................................................................ 4-6
4.2.6
Block Control Register 2 (BLKCON2) ................................................................................................................ 4-7
4.2.7
Block Control Register 3 (BLKCON3) ................................................................................................................ 4-8
4.2.8
Block Control Register 4 (BLKCON4) ................................................................................................................ 4-9
4.3 Description of Operation ............................................................................................................................................ 4-10
4.3.1
Program Run Mode............................................................................................................................................. 4-10
4.3.2
HALT Mode........................................................................................................................................................ 4-10
4.3.3
STOP mode......................................................................................................................................................... 4-11
4.3.3.1
STOP Mode When CPU Operates with Low-Speed Clock ................................................................................................. 4-11
4.3.3.2
STOP Mode When CPU Operates with High-Speed Clock................................................................................................. 4-12
4.3.4
Note on Return Operation from STOP/HALT Mode.......................................................................................... 4-13
4.3.5
Block Control Function ...................................................................................................................................... 4-14
Chapter 5
5. Interrupts............................................................................................................................................................................... 5-1
5.1 Overview ...................................................................................................................................................................... 5-1
5.1.1
Features................................................................................................................................................................. 5-1
5.2 Description of Registers ............................................................................................................................................... 5-2
5.2.1
List of Registers .................................................................................................................................................... 5-2
5.2.2
Interrupt Enable Register 1 (IE1).......................................................................................................................... 5-3
5.2.3
Interrupt Enable Register 2 (IE2).......................................................................................................................... 5-4
5.2.4
Interrupt Enable Register 3 (IE3).......................................................................................................................... 5-5
5.2.5
Interrupt Enable Register 4 (IE4).......................................................................................................................... 5-6
5.2.6
Interrupt Enable Register 5 (IE5).......................................................................................................................... 5-7
5.2.7
Interrupt Enable Register 6 (IE6).......................................................................................................................... 5-8
5.2.8
Interrupt Enable Register 7 (IE7).......................................................................................................................... 5-9
5.2.9
Interrupt Request Register 0 (IRQ0)................................................................................................................... 5-10
5.2.10 Interrupt Request Register 1 (IRQ1)................................................................................................................... 5-11
5.2.11 Interrupt Request Register 2 (IRQ2)................................................................................................................... 5-13
5.2.12 Interrupt Request Register 3 (IRQ3)................................................................................................................... 5-14
5.2.13 Interrupt Request Register 4 (IRQ4)................................................................................................................... 5-15
5.2.14 Interrupt Request Register 5 (IRQ5)................................................................................................................... 5-16
5.2.15 Interrupt Request Register 6 (IRQ6)................................................................................................................... 5-17
5.2.16 Interrupt Request Register 7 (IRQ7)................................................................................................................... 5-18
5.3 Description of Operation ............................................................................................................................................ 5-19
5.3.1
Maskable Interrupt Processing............................................................................................................................ 5-20
5.3.2
Non-Maskable Interrupt Processing ................................................................................................................... 5-20
5.3.3
Software Interrupt Processing............................................................................................................................. 5-20
5.3.4
Notes on Interrupt Routine ................................................................................................................................. 5-21
5.3.5
Interrupt Disable State ........................................................................................................................................ 5-24