參數(shù)資料
型號(hào): ML6421
廠商: Fairchild Semiconductor Corporation
英文描述: Triple Phase and Sinx/x Equalized, Low-Pass Video Filter(三相和Sinx/x相均衡的視頻低通濾波器)
中文描述: 三階段和氮化硅/ x均衡,低通視頻濾波器(三相和氮化硅/ x相均衡的視頻低通濾波器)
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 239K
代理商: ML6421
ML6421
8
FUNCTIONAL DESCRIPTION
The ML6421 single-chip Triple Video Filter IC is intended
for consumer and low cost professional video
applications. Each of the three channels incorporates an
input buffer amplifier, a sixth order lowpass filter, a first
order allpass equalizer, Sinx/x equalizer and an output
amplifier capable of driving 75y to ground.
The ML6421 can be driven by a DAC with Range down to
0V. When Range is low the input and output signal range
is 0.5V to 2.5V. When the input signal includes 0V, Range
should be tied high. In this case, an offset is added to the
input so that the output swing is kept between 0.5V to
2.5V. The output amplifier is capable of driving up to
24mA of peak current; therefore the output voltage should
not exceed 1.8V when driving 75y to ground.
APPLICATION GUIDELINES
OUTPUT CONSIDERATIONS
The triple filters have unity gain. The circuit has unity gain
(0dB) when connected to a 150y load, and a –6dB gain
when driving a 75y load via a 75y series output resistor.
The output may be either AC or DC coupled. For AC
coupling, the –3dB point should be 5Hz or less. There
must also be a DC path of -500y to ground for output
biasing.
INPUT CONSIDERATIONS
The input resistance is 4ky. The input may be either DC
or AC coupled. (Note that each input sources 80 to 125μA
of bias current). The ML6421 is designed to be directly
driven by a DAC. For current output video DACs, a 75y
or 150y resistor to ground may need to be added to the
DAC output (filter input).
Figure 4. ML6421 AC Coupled DC Bias Test Circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
IN
B
V
IN
A
RANGE
GNDA
GND
V
CC
A
V
OUT
A
V
OUT
B
GNDB
V
IN
C
GND
GNDC
V
CC
V
CC
C
V
OUT
C
V
CC
B
75
75
OUTA
OUTB
1
μ
F
0.1
μ
F
0.1
μ
F
100
μ
F
100
μ
F
3.1k
47
1k
85
47
85
3.1k
1k
INB
INA
0.1
μ
F
100
μ
F
1nF
1nF
1nF
1nF
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.001
μ
F
1
μ
F
100
μ
F
75
85
47
OUTC
3.1k
1k
INC
+5V
FB2
FB1
DC
BIAS
INPUT SIGNAL = 2V
P-P
INPUT
DECOUPLING
SUPPLY NOISE
CLAMPING
INPUT
TERMINATION
1
μ
F
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