參數(shù)資料
型號(hào): ML6423
廠商: Fairchild Semiconductor Corporation
英文描述: Dual S-Video Lowpass Filter with Phase and Sinx/x Equalization(相和Sinx/x相均衡的雙S-視頻低通濾波器)
中文描述: 雙S -視頻低通濾波器的相位和氮化硅/ x均衡(相和氮化硅/ x相均衡的雙第S -視頻低通濾波器)
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 273K
代理商: ML6423
ML6423
6
FUNCTIONAL DESCRIPTION
The ML6423 single-chip dual video filter is intended for
low cost professional and consumer video applications.
Each of the two channels incorporates an input buffer
amplifier, a 6th-order lowpass filter, a 1st-order allpass
equalizer, sinx/x equalizer and an output 2X gain
amplifier capable of driving 75
W
to ground. A third
output (B) is the sum of the A and C inputs and have the
identical output amplifier as the A and C channels.
The ML6423 can be driven by a DAC with RANGE down
to 0V. When RANGE is low the input range is 0.5V to
1.5V. When the input signal range is 0V to 0.1V, RANGE
should be tied high. In this case, an offset is added to the
input so that the output swing is kept between 0.5V to
2.5V. The output amplifier is capable of driving up to
24mA of peak current; therefore the output voltage should
not exceed 1.8V when driving 75
W
to ground.
APPLICATION GUIDELINES
OUTPUT & INPUT CONSIDERATIONS
The dual filters have 2X gain. The circuit has 2X gain
(6dB) when connected to a 150W load, and 0dB gain
when driving a 75
W
load via a 75
W
series output resistor.
The output may be either AC or DC coupled. For AC
coupling, the –3dB point should be 5Hz or less. There
must also be a DC path of
500
W
to ground for output
biasing. The ML6423-5 provides higher sink current to
better drive AC coupled loads.
The input resistance is 4k
W
. The input may be either DC
or AC coupled. (Note that each input sources 80 to 125μA
of bias current). The ML6423 is designed to be directly
driven by a DAC. For current output video DACs, a 75
W
or 150
W
resistor to ground may need to be added to the
DAC output (filter input).
Figure 4. ML6423 AC Coupled DC Bias Test Circuit
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
IN
A
RANGE
GNDA
V
CC
A
V
OUT
A
NC
V
CC
B
GNDB
V
IN
C
GND
GNDC
V
CC
NC
V
OUT
C
V
CC
C
V
OUT
B
75
V
OUT
A
1
μ
F
100
μ
F
+
0.1
μ
F
85
100
2.56k
1k
V
IN
A
+
100
μ
F
+
0.1
μ
F
100
μ
F
1nF
1nF
1nF
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
1nF
1
μ
F
75
85
100
V
OUT
C
75
V
OUT
B
2.56k
1k
V
IN
C
+5V
FB2
FB1
DC
BIAS
INPUT SIGNAL
= 1V
P-P
0.1
μ
F
1nF
INPUT
DECOUPLING
SUPPLY NOISE
CLAMPING
INPUT
TERMINATION
RESISTOR
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