參數(shù)資料
型號(hào): ML6510CQ-130
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 16/18頁(yè)
文件大小: 150K
代理商: ML6510CQ-130
ML6510
REV. 1.0 10/25/2000
7
LOAD[0-7]
LOAD[8-15]
tpp1 or tpp2
tSKEWR (or tSKEWB)
RCLKH
RCLKL
ML6510
CLKINH CLKINL
ML6510
SLAVE CHIP
(CM=1, CS=1)
DISTANCE <2"
LOAD[0-7]
LOAD[8-15]
PCB trace impedance
Z0 = 50
Lumped
CL ≤ 20pF
FBX
CLKX
ML6510-130
FIRST-ORDER
MATCHED LOADS
ML6510-130
GENERIC
LOAD
R2
One way trip delay < tRANGE/2
PCB trace impedance
Z0 = 50
Lumped
CLX ≤ 20pF
FBX
CLKX
LOAD
R2
R3
Length LX
PCB trace impedance
Z0 = 50
Lumped
CLY ≤ 20pF
FBY
CLKY
LOAD
R2
R3
One way trip delay < tRANGE/2
Length LY
|CLX – CLY| < 5pF
|LX – LY| < 4"
ZOX = ZOY
R3
PCB trace impedance
Z0 = 50
Lumped
CL ≤ 20pF
FBX
CLKX
ML6510-80
FIRST-ORDER
MATCHED LOADS
ML6510-80
GENERIC
LOAD
R1
One way trip delay < tRANGE/2
PCB trace impedance
Z0 = 50
Lumped
CLX ≤ 20pF
FBX
CLKX
LOAD
R1
Length LX
PCB trace impedance
Z0 = 50
Lumped
CLY ≤ 20pF
FBY
CLKY
LOAD
R1
One way trip delay < tRANGE/2
Length LY
|CLX – CLY| < 5pF
|LX – LY| < 4"
ZOX = ZOY
AC/Skew Characteristics Load Conditions
相關(guān)PDF資料
PDF描述
ML6510CQ-80 PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC44
ML6516241CR BICMOS SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48
ML6516244CT QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48
ML6516444CR BICMOS SERIES, 16-BIT DRIVER, TRUE OUTPUT, PDSO48
ML65244CS DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ML6510CQ80 制造商:Rochester Electronics LLC 功能描述:- Bulk
ML6510CQ-80 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:Series Programmable Adaptive Clock Manager (PACMan⑩)
ML6516244 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6516244CR 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs
ML6516244CT 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Buffer/Line Driver with 3-State Outputs