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參數(shù)資料
| 型號： | ML6553 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Bus Termination Regulator |
| 中文描述： | 總線終端穩(wěn)壓器 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 115K |
| 代理商： | ML6553 |
ML6553
PRODUCT SPECIFICATION
4
REV. 1.0.2 3/21/01
Functional Description
The ML6553 switching regulator is designed to sink and
source 1A load current and maintain a tight output voltage
regulation without the need for external feedback. Feedback
is accomplished internally by setting the average value of V
equal to V
CCQ/2
through a high gain error amp. The
ML6553 implements an open loop design that does not
require external loop compensation, providing a simplified
regulator design that can be used in cost sensitive applica-
tions.
L
Regulator Operation
Refer to the block diagram on the first page of this datasheet.
The oscillator/ramp block generates a 650kHz clock pulse
that is used to set the flip-flop. It also generates a 650kHz
ramp that the PWM comparator uses to reset the flip-flop.
When the flip-flop is set, the high side switch (Q1) is turned
on and the low side switch (Q2) is held off. In this state, the
voltage at V
L
is pulled up to PV
integrates and inverts. The resulting output voltage of the
error amp will decline until it intersects the rising voltage of
the ramp. When this occurs the flip-flop is reset. In the reset
state, the high side switch is off, the low side switch is on
and V
L
is pulled to DGND. The flip-flop will remain in the
reset state until the next clock pulse. A timing diagram is
shown in Figure 1.
DD
, which the error amp,
In the absence of a load, the duty cycle will be 50% if the
PV
DD
and V
CCQ
are the same. The average voltage at V
will be half the voltage applied to V
change will be zero. If the ML6553 needs to source current,
the duty cycle will increase, resulting in more current being
supplied to the load. If the ML6553 needs to sink current, the
duty will decrease, resulting in current being pulled from the
load and returned back to the PV
L
CCQ
, and the net current
DD
supply.
Figure 1. Timing Diagram
VL
Q
PWMCMP
RAMP
VINTEG
CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ML65541 | High Speed Octal Buffer/Line Drivers(高速八通道緩沖收發(fā)器) |
| ML65L541 | High Speed Octal Buffer/Line Drivers(高速八通道緩沖收發(fā)器) |
| ML6554CU | 3A Bus Termination Regulator |
| ML6554IU | 3A Bus Termination Regulator |
| ML6554 | 3A Bus Termination Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML6553CS1 | 功能描述:開關(guān)變換器、穩(wěn)壓器與控制器 Bus Termination RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開關(guān)頻率:1 MHz 工作溫度范圍: 安裝風格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| ML6553CS-1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Bus Termination Regulator |
| ML6553CS1X | 功能描述:開關(guān)變換器、穩(wěn)壓器與控制器 Bus Termination RoHS:否 制造商:Texas Instruments 輸出電壓:1.2 V to 10 V 輸出電流:300 mA 輸出功率: 輸入電壓:3 V to 17 V 開關(guān)頻率:1 MHz 工作溫度范圍: 安裝風格:SMD/SMT 封裝 / 箱體:WSON-8 封裝:Reel |
| ML6554 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:3A Bus Termination Regulator |
| ML65541 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:High Speed Octal Buffer/Line Drivers |
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