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參數(shù)資料
| 型號： | ML65F16244CT |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 99K |
| 代理商： | ML65F16244CT |
ML65F16244
REV. 1.0 10/25/2000
7
ARCHITECTURAL DESCRIPTION
The ML65F16244 is a 16-bit buffer/line driver with 3-state
outputs designed for 2.7V to 3.6V VCC operation. This
device is designed for Quad-Nibble, Dual-Byte or single
16-bit word memory interleaving operations. Each bank
has an independently controlled 3-state output enable pin
with output enable/disable access times of less than 5ns.
Each bank is configured to have four independent buffer/
line drivers.
Until now, these buffer/line drivers were typically
implemented in CMOS logic and made to be TTL
compatible by sizing the input devices appropriately. In
order to buffer large capacitances with CMOS logic, it is
necessary to cascade an even number of inverters, each
successive inverter larger than the preceding, eventually
leading to an inverter that will drive the required load
capacitance at the required frequency. Each inverter
stage represents an additional delay in the gating process
because in order for a single gate to switch, the input
must slew more than half of the supply voltage. The best
of these 16-bit CMOS buffers has managed to drive 50pF
load capacitance with a delay of 3ns.
Micro Linear has produced a 16-bit buffer/line driver with
a delay less than 2ns (at 3.3V) by using a unique circuit
architecture that does not require cascade logic gates.
The basic architecture of the ML65F16244 is shown in
Figure 6. In this circuit, there are two paths to the output.
One path sources current to the load capacitance where
the signal is asserted, and the other path sinks current
from the output when the signal is negated.
The assertion path is the Darlington pair consisting of
transistors Q1 and Q2. The effect of transistor Q1 is to
increase the current gain through the stage from input to
output, to increase the input resistance and to reduce
input capacitance. During an input low-to-high transition,
the output transistor Q2 sources large amount of current to
quickly charge up a highly capacitive load which in
effect reduces the bus settling time. This current is
specified as IDYNAMIC.
The negation path is also the Darlington pair consisting of
transistor Q3 and transistor Q4. With M1 connecting to
the input of the Darlington pair, Transistor Q4 then sinks a
large amount of current during the input transition from
high-to-low.
Inverter X2 is a helpful buffer that not only drives the
output toward the upper rail but also pulls the output to
the lower rail.
There are a number of MOSFETs not shown in Figure 6.
These MOSFETs are used to 3-state the buffers.
Figure 6. One Buffer Cell of the ML65F16244
OUT
OE
VCC
M1
IN
X1
X2
Q3
Q4
Q2
Q1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML65F16245 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Bidirectional Transceiver with 3-State Outputs |
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| ML65F16245CT | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Bidirectional Transceiver with 3-State Outputs |
| ML65F30MB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ML65 Series DC-DC Converter |
| ML65F30ML | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ML65 Series DC-DC Converter |
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