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參數(shù)資料
| 型號(hào)： | ML65F16245CR |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 106K |
| 代理商： | ML65F16245CR |
ML65F16245
REV. 1.0 10/25/2000
7
ARCHITECTURAL DESCRIPTION
The ML65F16245 is a 16-bit (dual-octal) non-inverting bus
transceiver with 3-state outputs designed for 2.7V to 3.6V
VCC operation. This device is designed for asynchronous
communication between data buses. The ML65F16245
can be used as two 8-bit transceivers or as one 16-bit
transceiver and can be designated as Port-A bus and Port-B
bus. The Direction and Output Enable controls are
designed to operate these configurations. The direction
control pin (iDIR) controls the direction of the data flow.
The output enable pin (1OE, 2OE) overrides the direction
control and disables both ports.
Until now, these transceivers were typically implemented
in CMOS logic and made to be TTL compatible by sizing
the input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an
inverter that will drive the required load capacitance at
the required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than
half of the supply voltage. The best of these 16-bit CMOS
buffers has managed to drive 50pF load capacitance with
a delay of 3ns.
Micro Linear has produced a 16-bit transceiver with a
delay less than 2ns (at 3.3V) by using a unique circuit
architecture that does not require cascade logic gates.
The basic architecture of the ML65F16245 is shown in
Figure 6. In this circuit, there are two paths to the output.
One path sources current to the load capacitance where
the signal is asserted, and the other path sinks current
from the output when the signal is negated.
The assertion path is the Darlington pair consisting of
transistors Q1 and Q2. The effect of transistor Q1 is to
increase the current gain through the stage from input to
output, to increase the input resistance and to reduce
input capacitance. During the transition state (the input
from low-to-high) the output transistor Q2 sources large
amount of current to quickly charge up a highly
capacitive load which in effect reduces the bus settling
time. This current is specified as IDYNAMIC.
The negation path is also the Darlington pair consisting of
transistor Q3 and transistor Q4. With M1 connecting to
the input of the Darlington pair, Transistor Q4 then sinks a
large amount of current during the input transition from
high-to-low.
Inverter X2 is a helpful buffer that not only drives the
output toward the upper rail but also pulls the output to
the lower rail.
There are a number of MOSFETs not shown in Figure 6.
These MOSFETs are used to 3-state the buffers.
OUT
OE
VCC
M1
IN
X1
X2
Q3
Q4
Q2
Q1
Figure 6. One Buffer Cell of the ML65F16245
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| ML65F16245CT | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:16-Bit Bidirectional Transceiver with 3-State Outputs |
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