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參數(shù)資料
| 型號(hào)： | ML65L541 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | High Speed Octal Buffer/Line Drivers(高速八通道緩沖收發(fā)器) |
| 中文描述： | 高速八路緩沖器/線路驅(qū)動(dòng)器（高速八通道緩沖收發(fā)器） |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | ML65L541 |
ML65541/ML65L541
REV. 1.0 10/25/2000
5
FUNCTIONAL DESCRIPTION
The ML65541 and ML65L541 are very high speed non-
inverting buffer/line drivers with three-state outputs which
are ideally suited for bus-oriented applications. They
provide a low propagation delay by using an analog
design approach (a high speed unity gain buffer), as
compared to conventional digital approaches. The
ML65541 and ML65L541 follow the pinout and
functionality of the industry standard FCT541 series of
buffer/line drivers and are intended to replace them in
designs where the propagation delay is a critical part of
the system design considerations. The ML65541 and
ML65L541 are capable of driving load capacitances
several times larger than their input capacitance. They are
configured so that the Ai inputs go to the Bi outputs when
enabled by
OE1
/
OE2
.
These unity gain analog buffers achieve low propagation
delays by having the output follow the input with a small
offset. The output rise and fall times will closely match
those of the input waveform. All inputs and outputs have
Schottky clamp diodes to handle undershoot or overshoot
noise suppression in unterminated applications. All
outputs have ground bounce suppression (typically
< 400mV), high drive output capability with almost
immediate response to the input signal, and low
output skew.
The I
OL
current drive capability of a buffer/line driver is
often interpreted as a measure of its ability to sink current
in a dynamic sense. This may be true for CMOS buffer/
line drivers, but it is not true for the ML65541 and
ML65L541. This is because their sink and source current
capability depends on the voltage difference between the
output and the input. The ML65541 can sink or source
more than 100mA to a load when the load is switching
due to the fact that during the transition, the difference
between the input and output is large. I
OL
is only
significant as a DC specification, and is 25mA.
Architectural Description
Until now, buffer/line drivers have been implemented in
CMOS logic and made to be TTL compatible by sizing
the input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an
inverter that will drive the required load capacitance at
the required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than
half of the supply voltage. The best of these CMOS buffers
has managed to drive a 50pF load capacitance with a
delay of 3.2ns. Micro Linear has produced an octal buffer/
line driver with a delay less than 1.7ns by using a unique
circuit architecture that does not require cascaded logic
gates. The ML65541 uses a feedback technique to
produce an output that follows the input. If the output
voltage is not close to the input, then the feedback
circuitry will source or sink enough current to the load
capacitance to correct the discrepancy.
Figure 5. One buffer cell of the ML65541
Q1
IN
OUT
Q2
Q7
R2
R6
R5
GND
R4
Q4
Q3
R1
R8
R3
Q5
Q6
R7
VCC
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| ML6554 | 3A Bus Termination Regulator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML65L541CK | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:High Speed Octal Buffer/Line Drivers |
| ML65L541CS | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:High Speed Octal Buffer/Line Drivers |
| ML65T541 | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:3.3V High Speed Octal Buffer/Line Driver |
| ML65T541CK | 制造商:MICRO-LINEAR 制造商全稱:MICRO-LINEAR 功能描述:3.3V High Speed Octal Buffer/Line Driver |
| ML65T541CK UP WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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