ML675001/ML67Q5002/ML67Q5003
10 Oki Semiconductor
April 2004, Rev 2.0
90
G10
GND
–
91
G11
VDD_IO
VDD
I/O power supply
–
92
G13
PIOD[2]
I/O
General port (with interrupt function)
XRAS_N
O
Row address strobe (SDRAM/EDO)
93
F11
PIOD[3]
I/O
General port (with interrupt function)
XSDCLK
O
Clock for SDRAM
94
F10
PIOD[4]
I/O
General port (with interrupt function)
XSDCS_N
O
Chip select for SDRAM
95
F12
PIOD[5]
I/O
General port (with interrupt function)
XSDCKE
O
Clock enable (SDRAM)
96
E12
BSEL[0]
I
Select boot device
–
97
F13
BSEL[1]
I
Select boot device
–
98
E10
PIOE[5]
I/O
General port (with interrupt function)
EXINT[0]
I
Interrupt input
99
D12
PIOE[6]
I/O
General port (with interrupt function)
EXINT[1]
I
Interrupt input
100
E13
PIOE[7]
I/O
General port (with interrupt function)
EXINT[2]
I
Interrupt input
101
E11
PIOE[8]
I/O
General port (with interrupt function)
EXINT[3]
I
Interrupt input
102
D11
PIOE[9]
I/O
General port (with interrupt function)
EFIQ_N
I
FIQ input
103
D13
PIOE[0]
I/O
General port (with interrupt function)
SCLK
I/O
SSIO clock
104
C12
PIOE[1]
I/O
General port (with interrupt function)
SDI
I
SSIO Serial Data In
105
D10
PIOE[2]
I/O
General port (with interrupt function)
SDO
O
SSIO Serial Data Out
106
C13
TDI
I
JTAG Data Input
–
107
B12
TDO
O
JTAG data out
–
108
B13
nTRST
I
JTAG reset
–
109
A13
PLLVDD
VDD
Power supply for PLL
–
110
A12
PLLGND
GND
GND for PLL
–
111
C11
CKO
O
Clock output
–
112
A11
JSEL
I
JTAG select
–
113
C10
TMS
I
JTAG mode select
–
114
B11
TCK
I
JTAG clock
–
115
A10
DRAME_N
I
DRAM enable
–
116
C9
CKOE_N
I
Clock out enable
–
117
B10
GND
–
118
A9
OSC0
I
Oscillation input pin
–
119
D9
OSC1_N
O
Oscillation output pin
–
120
B9
VDD_IO
VDD
IO power supply
–
121
A8
TEST
I
Test Mode
–
122
B8
PIOA[0]
I/O
General port (with interrupt function)
SIN
I
UART Serial Data In
123
D8
PIOA[1]
I/O
General port (with interrupt function)
SOUT
O
UART Serial Data Out
124
C8
AVDD
VDD
A/D Converter power supply
–
125
B7
VREFP
I
A/D Converter reference
–
126
D7
AIN[0]
I
A/D Converter analog input port
–
127
C7
AIN[1]
I
A/D Converter analog input port
–
128
A7
AIN[2]
I
A/D Converter analog input port
–
129
C6
AIN[3]
I
A/D Converter analog input port
–
130
D6
VREFN
GND
VREF return for A/D converter
131
B6
AGND
GND
GND for A/D Converter
–
132
B5
GND
–
133
A6
PIOA[2]
I/O
General port (with interrupt function)
CTS
I
UART Clear To Send
134
D5
VDD_IO
VDD
IO power supply
–
List of Pins (Continued)
Pin
Primary Function
Secondary Function
LQFP
BGA
Symbol
I/O
Description
Symbol
I/O
Description