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參數(shù)資料
| 型號(hào)： | ML69Q6500 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA272 |
| 封裝： | 15 X 15 MM, 0.65 MM PITCH, PLASTIC, LFBGA-272 |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大小： | 284K |
| 代理商： | ML69Q6500 |
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ML696500 and ML69Q6500
10 Oki Semiconductor
January 2005, Rev 1.1b
Preliminary
IDEA [2:0]
O
IDE controller address
Secondary
IDED [15:0]
I/O
IDE controller data
Secondary
IDERE_N
O
IDE controller read enable, Active-Low
Secondary
IDEWR_N
O
IDE controller write enable, Active-Low
Secondary
IDERDY
I
This allows the IDE controller's I/O cycle extension.
Secondary
IDERST_N
O
Reset signal, Active-Low
Secondary
IDECS1_N
O
IDE controller status/control select signal, Active-Low
Secondary
IDECS0_N
O
IDE controller data/command select signal, Active-Low
Secondary
IDEDREQ
I
IDE controller DMA request
Secondary
IDEDACK_N
O
IDE controller, DMA acknowledge, Active-Low
Secondary
IDEIRQ
I
IDE controller interrupt input
Secondary
IDENPCBRID
I
This detects the IDE primary cable ID.
Secondary
Flash
FD[7:0]
I/O
NAND Flash data
Primary
FRD_N
O
NAND Flash read enable, Active-Low
Primary
FWR_N
O
NAND Flash write enable, Active-Low
Primary
FRB
I
NAND Flash ready/busy (1 = ready, 0 = busy)
Primary
FALE
O
NAND Flash address latch enable
Primary
FCLE
O
NAND Flash command latch enable
Primary
USB
USB_DP
I/O
USB DP input/output
Primary
USB_DM
I/O
USB DM input/output
Primary
_REXT
I
USB REXT pin
Primary
USB_VOREF
O
VoRef pin for USB TEST
Primary
USB_ATEST [1:0]
O
USB ANALOG TEST pin 1-0
Primary
I2S Reception
ICLKOUTA/CLKOUT
O
I2S receive system clock
Secondary
SDA
I
I2S receive data
Secondary
WSA
I/O
I2S receive channel select
Secondary
SCLA/SCL
I/O
I2S receive transfer clock
Secondary
I2S Transmission
CKOUTD
O
I2S transmit system clock
Secondary
SDD
O
I2S transmit data
Secondary
WSD
I/O
I2S transmit channel select
Secondary
SCLD
I/O
I2S transmit transfer clock
Secondary
I2C
SDAT
I/O
I2C transmit/receive data
Primary
SCL
O
I2C clock output
Primary
SSIO
SSIOCK [1:0]
I/O
SSIO clock pins 0 and 1
Secondary
SSIORXD [1:0]
I
SSIO receive data input 1
Secondary
SSIOTXD [1:0]
O
SSIO transmit data output 1
Secondary
PWM
PWMOUT
O
PWM output
Primary
Pin Descriptions (Continued)
Symbol
I/O
Description
Primary/
Secondary
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