參數(shù)資料
型號: ML7001-02
廠商: OKI SEMICONDUCTOR CO., LTD.
元件分類: Codec
英文描述: Single Rail CODEC
中文描述: 單鐵編解碼器
文件頁數(shù): 5/19頁
文件大?。?/td> 144K
代理商: ML7001-02
Semiconductor
ML7000-01/02/03/ML7001-01/02/03
5/19
PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,
the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ is
inverted with respect to the output of AOUT–. Since these outputs provide differential drive of
an impedance of 1.2 k
W
, they can directly be connected to a handset using a piezoelectric
earphone or a line transformer. Refer to the application example.
V
DD
Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
R6 > 20 k
W
ZL > 1.2 k
W
Gain = VO/VI = 2
5
R7/R6
2
R6
R7
+
SG
+
SG
VFRO
PWI
AOUT–
AOUT+
ZL
Receive filter
VI
VO
20 k
W
20 k
W
相關(guān)PDF資料
PDF描述
ML7001-03 Single Rail CODEC
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ML7000-03 Single Rail CODEC
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ML7001-03MB 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:Single Rail CODEC