參數(shù)資料
型號(hào)： ML7021
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： Echo Canceler
中文描述： 回聲消除器
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 244K
代理商： ML7021
5
Semiconductor
ML7021
(2/4)
Pin
5
Symbol
ATT
Type
I
Description
6
INT
I
7
IRLD
O
8
SIN
I
9
RIN
I
10
SCK
I
Control for the ATT function.
This pin prevents howling by attenuators (ATT) for the RIN input and SOUT
output.
If there is input only to RIN, the ATT for the SOUT output is activated.
If there is no input to SIN, or if there is input to both SIN and RIN, the ATT
for the RIN input is activated.
Either the ATT for the RIN output or the ATT for the SOUT is always
activated in all cases, and the attenuation of ATT is 6 dB.
Single Chip or Master Chip in a Cascade Connection
"H": ATT OFF
"L": ATT ON
"L" is recommended if performing echo cancellation.
Slave Chip in a Cascade Connection
Fixed at "L"
This input signal is loaded in synchronization with the falling edge of the
INT
signal or the rising edge of the
RST
signal.
Interrupt signal which starts 1 cycle (8 kHz) of the signal processing.
Signal processing starts when "H"-to-"L" transition is detected.
Single Chip or Master Chip in a Cascade Connection
Connect the
IRLD
pin.
Slave Chip in a Cascade Connection
Connect the
IRLD
pin of the master chip.
INT
input is invalid for 100
m
s after reset due to initialization.
Refer to the control pin connection example.
Load detection signal output when the SIN and RIN serial input data is
loaded in the internal registers.
Single Chip
Connect to the
INT
pin.
Master Chip in a Cascade Connection
Connect to the
INT
pin of the master chip and all the slave chips.
Slave Chip in a Cascade Connection
Leave open.
Refer to the control pin connection example.
Transmit serial data.
Input the PCM signal synchronized to SYNC and SCK. Data is read in at
the falling edge of SCK.
Receive serial data.
Input the PCM signal synchronized to SYNC and SCK. Data is read in at
the falling edge of SCK.
Clock input for transmit/receive serial data.
This pin uses the external SCK or the SCKO.
Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).
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