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參數(shù)資料
| 型號： | ML9211 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 56-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming |
| 中文描述： | 56位雙/三層（1 / 2的責任/ 1 / 3的責任）變頻控制器/數(shù)字調(diào)光驅(qū)動器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 230K |
| 代理商： | ML9211 |
Semiconductor
ML9211
6/19
PIN DESCRIPTIONS
Symbol
QFP-1
*
Type
Description
V
DISP
65, 80
—
Power supply pins for VFD driver circuit.
These should be connected externally.
Power supply pin for logic drive.
D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the
logic circuit. These should be connected externally.
Segment (anode) signal output pins for a VFD tube. These pins can be directly
connected to the VFD tube. External circuit is not required.
I
OH
￡
–5 mA
Segment (anode) signal output pins for a VFD tube.These pins can be directly
connected to the VFD tube. External circuit is not required.
I
OH
￡
–10 mA
Inverted Grid signal output pins. For pre-driver, the external circuit is required.
I
OL
￡
10 mA
V
DD
D-GND
L-GND
25
—
—
—
24, 40
33
SEG1 to 37
42 to 64,
66 to 79
O
SEG38 to 56 1 to 19
O
GRID2
GRID3
21
22
O
CS
29
I
Chip select input pin.
Data is not transferred when CS is set to a Low level.
Shift clock input pin.
Serial data shifts at the rising edge of the CLOCK.
Serial data input pin (positive logic).
Data is input to the shift register at the rising edge of the CLOCK signal.
Duplex/Triplex operation select input pin.
Duplex (1/2 duty) operation is selected when this pin is set to V
DD
.
Triplex (1/3 duty) operation is selected when this pin is set to L-GND.
Master/Slave mode select input pin.
Master mode is selected when this pin is set to V
DD
.
Slave mode is selected when this pin is set to L-GND.
Dimming pulse input.
When the slave mode is selected, connect this pin to the master side DIM
OUT pin at the slave mode. The pulse width of the all segment output are
controlled by a input pulse width of DIM IN.
When the master mode is selected, the input level of this pin is ignored.
Connect this pin to V
DD
or L-GND at the master mode. The pulse width of the
all grids and segment outputs are controlled by a built-in 10-bit dimming circuit.
CLOCK
30
I
DATA IN
31
I
DUP/
TRI
35
I
M/
S
36
I
DIM IN
26
I
SYNC IN 2
28
I
Synchronous signal input.
When the slave mode is selected, connect these pins to the master side SYNC
OUT 1 and 2 pins.
When the master mode is selected, the input level of these pins are ignored.
Connect these pins to V
DD
or L-GND at the master mode.
Dimming pulse output.
Connect this pin to the slave side DIM IN pin.
DIM OUT
39
O
QFP-2
*
63 78
23
22, 38
31
40 to 62,
64 to 77
79, 80,
1 to 17
19
20
27
28
29
33
34
24
26
37
20
18
GRID1
SYNC IN 1
27
25
Pin
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