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參數(shù)資料
| 型號(hào)： | ML9261 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver |
| 中文描述： | 60位真空熒光顯示管網(wǎng)/陽極驅(qū)動(dòng) |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 160K |
| 代理商： | ML9261 |
Semiconductor
ML9261/62
6/16
PIN DESCRIPTION
Symbol
Description
CLK
Shift register clock input pin.
Shift register reads data from DIN while the CLK pin is low and the data in the shift register
is shifted from one stage to the next stage at the rising edge of the clock.
Type
I
Serial data input pin of the shift register.
Display data (positive logic) is input in the DIN pin in synchronization with clock.
DIN
I
Serial data output pin of the shift register.
Data is output from the DOUT pin in synchronization with the CLK signal.
DOUT
O
Latch strobe input pin.
The contents of the parallel outputs (PO1 to PO60) of the shift register are read at the rising
edge of LS (edge-triggered). When the CLK rises while LS is high, the parallel outputs
(PO1 to PO60) and latch outputs (O1 to O60) go low.
LS
I
Clear input pin with a built-in pull-down resistor.
The
CL
pin is normally set high.
If the
CL
pin is high and the CHG pin is low, the driver outputs (HV01 to HV60) are in phase
with the corresponding register outputs (O1 to O60).
If the
CL
pin is high and the CHG pin is high, the driver outputs (HV01 to HV60) are high
irrespective of the states of the register outputs.
If the
CL
pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and register outputs.
This allows display blanking to be set.
CL
I
Input for testing (with a pull-down resistor).
The
CL
pin is normally set low.
If the CHG pin is low and the
CL
pin is high, the driver outputs (HV01 to HV60) are in phase
with the corresponding register outputs (O1 to O60).
If the CHG pin is low and the
CL
pin is low, the driver outputs (HV01 to HV60) are low
irrespective of the states of the register outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
register outputs.
This provides the easy testing of all lights after final assembly.
CHG
I
High voltage driver outputs for driving VFD tube.
If the
CL
pin is high and the CHG pin is low, the driver outputs are in phase with the
corresponding register outputs (O1 to O60).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
Power supply pin for driver circuits of VFD tube
Power supply pin for logic
GND pin for driver circuits of a VFD tube.
Since the D-GND is not be connected to L-GND, connect this pin to the external L-GND.
GND pin for the logic circuits.
Since the L-GND pin is not be connected to D-GND, connect this pin to the external D-GND.
VHO1-60
O
V
DISP
V
DD
D-GND
L-GND
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相關(guān)代理商/技術(shù)參數(shù) |
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| ML9261A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver |
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| ML9266 | 制造商:MINILOGIC 制造商全稱:MINILOGIC 功能描述:Step-up DC/DC converter |
| ML9266MRG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Step-up DC/DC converter |
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