參數(shù)資料
型號: ML9262
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
中文描述: 60位真空熒光顯示管網(wǎng)/陽極驅(qū)動
文件頁數(shù): 10/17頁
文件大?。?/td> 160K
代理商: ML9262
Semiconductor
ML9261/62
10/16
CLK-LS Setup Time
LS-CLK Setup Time
ns
ns
ns
ns
LS-CHG Setup Time
LS-
CL
Setup Time
LS Pulse Width
50
50
50
50
50
ns
ns
ns
ns
m
s
m
s
ns
m
s
m
s
m
s
50
50
80
10
10
50
1.0
1.0
1.0
CHG Pulse Width
CL
Pulse Width
DOUT Delay time
Driver Output Slew Rate
m
s
m
s
5.0
5.0
t
H
(CLK-D)
t
SU
(CLK-LS)
t
SU
(LS-CLK)
t
SU
(L-CLK)
t
H
(CLK-L)
t
SU
(LS-CHG)
t
SU
(LS-
CL
)
t
W
(LS)
t
W
(CHG)
t
W
(
CL
)
t
PD
, t
PRD
t
DLH
t
DHL
t
DRHL
t
THL
t
TLH
Driver Output Delay Time
(V
DD
=4.5 to 5.5V, V
DISP
=40V, Ta=–40 to +85°C)
Condition
DIN Hold Time
Max.
150
Min.
80
50
Unit
ns
Symbol
t
W
(CLK)
t
SU
(D-CLK)
Parameter
DIN Setup Time
ns
CLK Pulse Width
During normal operation
At display data reset
At display data reset
CLK-LS Hold Time
Load: 30pF
Load: 2.0k
W
resistance in
parallel with 20pF capacitance
Load: 2.0k
W
resistance in
parallel with 20pF capacitance
AC Characteristics-1
AC Characteristics-2
CLK-LS Setup Time
LS-CLK Setup Time
ns
ns
ns
ns
LS-CHG Setup Time
LS-
CL
Setup Time
LS Pulse Width
50
50
50
50
50
ns
ns
ns
ns
m
s
m
s
ns
m
s
m
s
m
s
50
50
80
10
10
50
3.0
3.0
3.0
CHG Pulse Width
CL
Pulse Width
DOUT Delay time
Driver Output Slew Rate
m
s
m
s
5.0
5.0
t
H
(CLK-D)
t
SU
(CLK-LS)
t
SU
(LS-CLK)
t
SU
(L-CLK)
t
H
(CLK-L)
t
SU
(LS-CHG)
t
SU
(LS-
CL
)
t
W
(LS)
t
W
(CHG)
t
W
(
CL
)
t
PD
, t
PRD
t
DLH
t
DHL
t
DRHL
t
THL
t
TLH
Driver Output Delay Time
(V
DD
=3.0 to 3.6V, V
DISP
=40V, Ta=–40 to +85°C)
Condition
DIN Hold Time
Max.
150
Min.
80
Unit
ns
Symbol
t
W
(CLK)
Parameter
50
ns
t
SU
(D-CLK)
DIN Setup Time
CLK Pulse Width
During normal operation
At display data reset
At display data reset
CLK-LS
Load: 30pF
Load: 2.0k
W
resistance in
parallel with 20pF capacitance
Load: 2.0k
W
resistance in
parallel with 20pF capacitance
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