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參數(shù)資料
| 型號： | MLT04GS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Four-Channel, Four-Quadrant Analog Multiplier |
| 中文描述： | ANALOG MULTIPLIER OR DIVIDER, 8 MHz BAND WIDTH, PDSO18 |
| 封裝： | SOIC-18 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 428K |
| 代理商： | MLT04GS |
–3–
REV. B
FUNCT IONAL DE SCRIPT ION
T he MLT 04 is a low cost quad, 4-quadrant analog multiplier with
single-ended voltage inputs and voltage outputs. T he functional
block diagram for each of the multipliers is illustrated in Figure 3.
Due to packaging constraints, access to internal nodes for externally
adjusting scale factor, output offset voltage, or additional summing
signals is not provided.
Figure 3. Functional Block Diagram of Each MLT04
Multiplier
Each of the MLT 04’s analog multipliers is based on a Gilbert cell
multiplier configuration, a 1.23 V bandgap reference, and a unity-
connected output amplifier. Multiplier scale factor is determined
through a differential pair/trimmable resistor network external to
the core. An equivalent circuit for each of the multipliers is shown
in Figure 4.
Figure 4. Equivalent Circuit for the MLT04
Details of each multiplier’s output-stage amplifier are shown in
Figure 5. T he output stages idles at 200
μ
A, and the resistors in
series with the emitters of the output stage are 25
. T he output
stage can drive load capacitances up to 500 pF without oscillation.
For loads greater than 500 pF, the outputs of the MLT 04 should
be isolated from the load capacitance with a 100
resistor.
Figure 5. Equivalent Circuit for MLT04 Output Stages
ANALOG MULT IPLIE R E RROR SOURCE S
Multiplier errors consist primarily of input and output offsets, scale
factor errors, and nonlinearity in the multiplying core. An expres-
sion for the output of a
real
analog multiplier is given by:
V
O
=
(
K
+
K
){(
V
X
+
X
OS
)(
V
Y
+
Y
OS
)
+
Z
OS
+
f
(
X
,
Y
)}
where:
K
=
Multiplier Scale Factor
K
=
Scale Factor Error
V
X
=
X -Input Signal
X
OS
=
X -Input Offset Voltage
V
Y
=
Y-Input Signal
Y
OS
=
Y-Input Offset Voltage
Z
=
Multiplier Output Offset Voltage
(X
,
Y
) =
Nonlinearity
Executing the algebra to simplify the above expression yields
expressions for all the errors in an analog multiplier:
T erm
Description
Dependence on Input
K V
X
V
Y
T rue Product
Goes to Zero As Either or
Both Inputs Go to Zero
K V
Y
V
Y
V
X
Y
OS
Scale-Factor Error
Goes to Zero at V
X
, V
Y
= 0
Proportional to V
X
Linear “X ” Feedthrough
Due to Y-Input Offset
V
Y
X
OS
Linear “Y” Feedthrough
Due to X -Input Offset
Proportional to V
Y
X
OS
Y
OS
Output Offset Due to X -,
Y-Input Offsets
Independent of V
X
, V
Y
Z
OS
(X , Y)
Output Offset
Independent of V
X
, V
Y
Depends on Both V
, V
.
Contains T erms Dependent
on V
, V
, T heir Powers
and Cross Products
Nonlinearity
As shown in the table, the primary static errors in an analog
multiplier are input offset voltages, output offset voltage, scale
factor, and nonlinearity. Of the four sources of error, only two are
externally trimmable in the MLT 04: the X - and Y-input offset
voltages. Output offset voltage in the MLT 04 is factory-trimmed to
±
50 mV, and the scale factor is internally adjusted to
±
2.5% of full
scale. Input offset voltage errors can be eliminated by using the
optional trim circuit of Figure 6. T his scheme then reduces the net
error to output offset, scale-factor (gain) error, and an irreducible
nonlinearity component in the multiplying core.
Figure 6. Optional Offset Voltage Trim Configuration
MLT04
V
CC
V
EE
W
OUT
25
25
V
CC
INTERNAL
BIAS
X
IN
GND
Y
IN
V
EE
W
OUT
22k
200μA
200μA
22k
22k
200μA
200μA
200μA
200μA
SCALE
FACTOR
50k
–V
S
50k
+V
S
±100mV
FOR X
OS
, Y
OS
TRIM
CONNECT TO SUM
NODE OF AN EXT OP AMP
I
0.4
+V
S
–V
S
X1, X2, X3, X4
G1, G2, G3, G4
Y1, Y2, Y3, Y4
W1, W2, W3, W4
MLT04
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