參數(shù)資料
型號: MM24128-BRBN6T
廠商: 意法半導(dǎo)體
元件分類: EEPROM
英文描述: 256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines
中文描述: 一百二十八分之二百五十六千位串行總線EEPROM,帶有集成電路芯片啟用三線
文件頁數(shù): 1/19頁
文件大?。?/td> 117K
代理商: MM24128-BRBN6T
1/19
PRELIMINARY DATA
February 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24256-B
M24128-B
256/128 Kbit Serial
I
C Bus EEPROM
With Three Chip Enable Lines
I
Compatible with I
2
C Extended Addressing
I
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
I
Single Supply Voltage:
– 4.5V to 5.5V for M24xxx-B
– 2.5V to 5.5V for M24xxx-BW
– 1.8V to 3.6V for M24xxx-BR
I
Hardware Write Control
I
BYTE and PAGE WRITE (up to 64 Bytes)
I
RANDOM and SEQUENTIAL READ Modes
I
Self-Timed Programming Cycle
I
Automatic Address Incrementing
I
Enhanced ESD/Latch-Up Behavior
I
100000 Erase/Write Cycles (minimum)
I
40 Year Data Retention (minimum)
DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).
These memory devices are compatible with the
I
2
C extended memory standard. Thisis a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I
2
C bus definition.
Figure 1. Logic Diagram
AI02809
SDA
VCC
M24256-B
M24128-B
WC
SCL
VSS
3
E0-E2
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
PSDIP8 (BN)
0.25 mm frame
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
8
1
8
1
8
1
TSSOP14 (DL)
169 mil width
14
1
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