參數(shù)資料
型號: MM54HC138J
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 編、解碼器及復用、解復用
英文描述: HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16
封裝: DIP-16
文件頁數(shù): 1/4頁
文件大?。?/td> 114K
代理商: MM54HC138J
TLF5120
MM54HC138MM74HC138
3-to-8
Line
Decoder
January 1988
MM54HC138MM74HC138
3-to-8 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol-
ogy and is well suited to memory address decoding or data
routing applications The circuit features high noise immuni-
ty and low power consumption usually associated with
CMOS circuitry yet has speeds comparable to low power
Schottky TTL logic
The MM54HC138MM74HC138 has 3 binary select inputs
(A B and C) If the device is enabled these inputs deter-
mine which one of the eight normally high outputs will go
low Two active low and one active high enables (G1 G2A
and G2B) are provided to ease the cascading of decoders
The decoder’s outputs can drive 10 low power Schottky TTL
equivalent loads and are functionally and pin equivalent to
the 54LS13874LS138 All inputs are protected from dam-
age due to static discharge by diodes to VCC and ground
Features
Y
Typical propagation delay 20 ns
Y
Wide power supply range 2V – 6V
Y
Low quiescent current 80 mA maximum (74HC Series)
Y
Low input current 1 mA maximum
Y
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
TLF5120 – 1
Order Number MM54HC138
or MM74HC138
Truth Table
Inputs
Outputs
Enable
Select
G1
G2
C
B
AY0Y1Y2Y3Y4Y5Y6Y7
X
H
X
HHHHHHHH
L
X
HHHHHHHH
H
L
H
HHHHHH
H
L
H
L
HHHHHH
H
L
H
L
HH
L
H
HHHH
H
L
H
HLH
H
L
H
L
H
HHH
L
HHH
H
L
H
L
H
HHHHH
L
H
L
H
L
H
HHHHH
L
H
L
H
HHHHHHH
L
G2eG2AaG2B
Hehigh level Lelow level Xedon’t care
TLF5120 – 2
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A
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相關代理商/技術參數(shù)
參數(shù)描述
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