參數(shù)資料
型號: MM74C165
廠商: Fairchild Semiconductor Corporation
英文描述: Parallel-Load 8-Bit Shift Register
中文描述: 并聯(lián)負載8位移位寄存器
文件頁數(shù): 4/6頁
文件大小: 50K
代理商: MM74C165
www.fairchildsemi.com
4
M
AC Electrical Characteristics
(Note 2)
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise noted
Note 2:
AC Parameters are guaranteed by DC correlated testing.
Note 3:
Capacitance is guaranteed by periodic testing.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note
AN-90.
Switching Time Waveform
Note A:
The remaining six data and the serial input are LOW.
Note B:
Prior to test, HIGH level data is loaded into the P7 input.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd0
, t
pd1
Propagation Delay Time to a Logical “0” or
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
(Note 3)
(Note 4)
200
80
400
200
ns
ns
Logical “1” from Clock or Load to Q or Q
t
pd0
, t
pd1
Propagation Delay Time to a Logical “0” or
200
80
400
200
ns
ns
Logical “1” from H to Q or Q
t
S
Clock Inhibit Set-up Time
150
60
50
75
30
25
ns
ns
ns
t
S
Serial Input Set-up Time
30
50
30
15
0
0
ns
ns
ns
t
H
Serial Input Hold Time
t
S
Parallel Input Set-Up Time
150
60
50
75
30
0
ns
ns
ns
t
H
Parallel Input Hold Time
30
0
ns
ns
ns
t
W
Minimum Clock Pulse Width
70
30
200
100
t
W
Minimum Load Pulse Width
85
30
6
180
90
ns
ns
MHz
f
MAX
Maximum Clock Frequency
2.5
5
12
MHz
μ
s
μ
s
pF
pF
t
r
, t
f
Maximum Clock Rise and Fall Time
10
5
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
5
65
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