參數(shù)資料
型號: MM74C175N
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad D-Type Flip-Flop
中文描述: CMOS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-16
文件頁數(shù): 1/6頁
文件大小: 55K
代理商: MM74C175N
October 1987
Revised January 1999
M
1999 Fairchild Semiconductor Corporation
DS005900.prf
www.fairchildsemi.com
MM74C175
Quad D-Type Flip-Flop
General Description
The MM74C175 consists of four positive-edge triggered D-
type flip-flops implemented with monolithic CMOS technol-
ogy. Both are true and complemented outputs from each
flip-flop are externally available. All four flip-flops are con-
trolled by a common clock and a common clear. Informa-
tion at the D-type inputs meeting the set-up time
requirements is transferred to the Q outputs on the posi-
tive-going edge of the clock pulse. The clearing operation,
enabled by a negative pulse at Clear input, clears all four Q
outputs to logical “0” and Q's to logical “1”.
All inputs are protected from static discharge by diode
clamps to V
CC
and GND.
Features
I
Wide supply voltage range:
I
Guaranteed noise margin:
I
High noise immunity:
3V to 15V
1.0V
0.45 V
CC
(typ.)
Fan out of 2 driving 74L
I
Low power TTL compatibility:
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
Each Flip-Flop
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
=
Transition from LOW-to-HIGH level
NC
=
No Change
Order Number
MM74C175M
MM74C175N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs
Outputs
Clear
Clock
D
Q
Q
L
X
X
L
H
H
H
H
L
H
L
L
H
H
H
X
NC
NC
H
L
X
NC
NC
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