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參數(shù)資料
| 型號： | MM74C193N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter |
| 中文描述： | CMOS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 62K |
| 代理商： | MM74C193N |
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M
AC Electrical Characteristics
(Note 2)
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise noted
Note 2:
AC Parameters are guaranteed by DC correlated testing.
Note 3:
Capacitance is guaranteed by periodic testing.
Note 4:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Application Note AN-90.
Cascading Packages
Guaranteed Noise Margin
as a Function of V
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay
Time to Q from Count Up or Down
Propagation Delay
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
(Note 3)
250
100
120
400
160
200
ns
ns
ns
t
pd
Time to Q Borrow from Count Down
Propagation Delay
Time to Carry from Count Up
50
120
50
80
200
80
ns
ns
ns
t
pd
t
S
Time Prior to Load
that Data Must be Present
Minimum Clear Pulse Width
100
30
300
160
50
480
ns
ns
ns
t
W
120
100
40
190
160
65
ns
ns
ns
t
W
Minimum Load Pulse Width
t
pd0
t
pd1
t
W
Propagation Delay
Time to Q from Load
Minimum Count Pulse Width
300
120
120
480
190
200
ns
ns
ns
35
4
10
80
ns
MHz
MHz
μ
s
μ
s
pF
f
MAX
Maximum Count Frequency
2.5
6
t
r
t
f
C
IN
C
PD
Count Rise and Fall Time
15
5
Input Capacitance
5
Power Dissipation Capacitance
(Note 4)
100
pF
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