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參數(shù)資料
| 型號(hào)： | MM74C48N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | BCD-to-7 Segment Decoder |
| 中文描述： | CMOS SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 57K |
| 代理商： | MM74C48N |
October 1987
Revised January 1999
M
1999 Fairchild Semiconductor Corporation
DS005883.prf
www.fairchildsemi.com
MM74C48
BCD-to-7 Segment Decoder
General Description
The MM74C48 BCD-to-7 segment decoder is a monolithic
complementary MOS (CMOS) integrated circuit con-
structed with N- and P-channel enhancement transistors.
Seven NAND gates and one driver are connected in pairs
to make binary-coded decimal (BCD) data and its comple-
ment available to the seven decoding AND-OR-INVERT
gates. The remaining NAND gate and three input buffers
provide test-blanking input/ripple-blanking output, and rip-
ple-blanking inputs.
Features
I
Wide supply voltage range:
I
Guaranteed noise margin:
I
High noise immunity:
3.0V to 15V
1.0V
0.45 V
CC
(typ.)
I
Low power TTL compatibility:
fan out of 2 driving 74L
I
High current sourcing output (up to 50 mA)
I
Ripple blanking for leading or trailing zeros (optional)
I
Lamp test provision
Ordering Code:
Connection Diagrams
Pin Assignments for DIP
Top View
Segment Identification
Numerical Designations
and Resultant Displays
Order Number
MM74C48N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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