Physical Dimens" />
參數(shù)資料
型號(hào): MM74HC02MX
廠商: Fairchild Semiconductor
文件頁數(shù): 8/9頁
文件大小: 0K
描述: IC GATE NOR QUAD 2-INP 14-SOIC
標(biāo)準(zhǔn)包裝: 1
系列: 74HC
邏輯類型: 或非門
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 6 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 5.2mA,5.2mA
邏輯電平 - 低: 0.5 V ~ 1.8 V
邏輯電平 - 高: 1.5 V ~ 4.2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 15ns @ 6V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1208 (CN2011-ZH PDF)
其它名稱: MM74HC02MXDKR
1983 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HC02 Rev. 1.3.0
8
MM74HC02
Quad
2-Input
NOR
Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
14
8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A)
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30
5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35
2.54
3.81
3.17
8.82
(1.74)
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